Good FPGA Starting Point?

[mfro]

I don't know if the other vendors have a similar feature but being able to debug the actual hardware at full speed is pretty slick.  This feature may push toward Xilinx boards like those from Digilent.  I have only used it on the retired Nexys 4 DDR board now known as the Nexys A7 board.

Intel/Altera has SignalTap which is essentially the same thing.

I do have a scope but basically never use it for FPGA development (except maybe to measure real timing of badly documented peripherials).

The workflow is to develop a specification, implement it in HDL, simulate with ModelSim (or ghdl) and correct all the flaws you haven't seen during spec time and finally get the timing constraints right. Until then, Quartus really didn't see my sources (except for maybe occasional checks if the code compiles there as well).
Only after everything red in the TimeQuest has been eliminated, the configuration goes to the chip for the first time. It then usually just works (and only needs SignalTap in very rare tenacious cases).

The turnaround times of Analysys/Synthesis and Fitter are just way too long to work "evolutionary" with the real hardware. Even moderately complex designs take like 20 minutes to compile on a reasonably fast machine and that is way too long to "keep up the flow".

[NorthGuy]

I don't know if the other vendors have a similar feature but being able to debug the actual hardware at full speed is pretty slick.  This feature may push toward Xilinx boards like those from Digilent.

ILA is not a separate hardware, just a design running on the FPGA and sampling the signals from your design. The data is collected through JTAG, which is 30 MHz with some overhead, so it cannot do much at full speed. If you have a better communication channel to your PC (such as Gigabit Ethernet or USB 3), you can roll out your own ILA which will be much more capable.

[asmi]

Intel/Altera has SignalTap which is essentially the same thing

Is it free like ILA is? Antel loves charging for everything
I mostly use ILA when I need to verify interface with external devices. Internal stuff is ironed out with simulations. Xilinx also provides free "JTAG to AXI Master" IP which allows probing system buses in real time on a running system - this is very useful in CPU-less designs when you can't use debugger's "Memory view" (or whatever it's called in Eclypse), or when a bus of interest is not connected to CPU.

[asmi]

ILA is not a separate hardware, just a design running on the FPGA and sampling the signals from your design. The data is collected through JTAG, which is 30 MHz with some overhead, so it cannot do much at full speed. If you have a better communication channel to your PC (such as Gigabit Ethernet or USB 3), you can roll out your own ILA which will be much more capable.

It collects data at full speed (until it fills the sample buffer), you just can't stream it to PC in real time. But the latter is rarely needed anyway, certainly not for debugging - you can't really make sense of such stream of data in real time anyway.

[hinxx]

I just started playing with the FPGAs as well. I wanted to learn Verilog, not VHDL or SystemVerilog at this point. Been warned of the steep learning curve, but after a couple of weeks I'm quite happy with where I am.

I went with OLIMEX iCE40HX1K-EVB https://www.olimex.com/Products/FPGA/iCE40/iCE40HX1K-EVB/open-source-hardware since open source is kind of my cup of tea. Along with that I got their ADC and digital IO boards, and a programmer (not really necessary since you can use RPi or some other Arduino board for that). They also provide a guide on how to get the complete (open source) toolchain up and running ; it worked as advertised for me on Linux. I did not even download Lattice iCEcube2 tool. iverilog and GTKwave is serving me well for now, along with any text editor I feel like using that day..

OLIMEX github provides programming SW tool and a Verilog blinky LED demo I started off: https://github.com/OLIMEX/iCE40HX1K-EVB/tree/master/demo/ice40hx1k-evb.

Then I stumbled upon some tutorials at http://hdlexpress.com/Verilog/VT.html and went through couple of initial videos and did the examples (very important to actually do the lessons!). I like how Kirk is presenting material with very little bloat in those videos.. I did not finish the complete lecture series, I'm still at part 5 lessons; I was to eager to start hacking at the Verilog now that I understand the syntax and a little bit of modeling and simulating.

What got me interested was discovery of this on this forum: https://www.eevblog.com/forum/fpga/verilog-rs232-uart-and-rs232-debugger-source-code-and-educational-tutorial/msg2801388/?topicseen#msg2801388 by BrianHG. Managed to get it working on Olimex board, and now it talks to my PC based CLI tool that can talk to FPGA over UART (not being a Pascal fan myself I went with homebrew C code around FTDI DXX2 library). It was a great Verilog code for me to learn from, being a complete starter. If you can believe I managed to get my FPGA to talk to the SRAM on the EVB, plus I'm now doing SRAM memory 16-bit word reads/writes over the UART . Gotta have comms and memory under control before you can do more .

I'll be tinkering with RLE and some OLED displays for fun next.

[mfro]

Intel/Altera has SignalTap which is essentially the same thing

Is it free like ILA is? Antel loves charging for everything

It is. At least for the consumer FPGAs I'm dealing with.

[rstofer]

Earlier in the thread I was talking about the LC3 RISC project and my use of 100T versions of the Artix 7 and how they are probably overkill.  So, I drug out my Basys3 35T board, clipped off some unavailable signals (8 digit 7 seg display versus 4 digit, color LEDs, etc) and, voila', it fits.  The big user is BlockRAM and it uses 32 of the 50 available blocks.  On the 100T 32 of 100 blocks.  Nevertheless, as an educational project, the LC3 will easily fit in the 35T devices.

Attached is the utilization summary.  Look at how few FFs and LUTs are used.  Remember, this is a pretty significant RISC processor with 64k of 16 bit memory complete with a privilege control system.

Google for LC3 Appendix A and LC3 Appendix C

There's a lot of logic in an Artix 7 35T.  My projects tend to push the limits of BlockRAM, not logic.  External memory is one solution but it takes a lot of pins.

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