GOWIN Semi FPGA - BRAM IP usage

[up8051]

Hi,
 I have Tang Nano module with Gowin FPGA GW1N-1-LV.
 In my project I would like to use "Semi Dual Port RAM".
I can generate IP (by IP generator) but I confused about signal names and where is write signal

PORT A is for Write for B is for Read:

Code: [Select]

component Gowin_SDPB
    port (
        dout: out std_logic_vector(7 downto 0);
        clka: in std_logic;
        cea: in std_logic;
        reseta: in std_logic;
        clkb: in std_logic;
        ceb: in std_logic;
        resetb: in std_logic;
        oce: in std_logic;
        ada: in std_logic_vector(8 downto 0);
        din: in std_logic_vector(7 downto 0);
        adb: in std_logic_vector(8 downto 0)
    );
end component;
The figure suggests that the OCE signal is for Port A.
I would rather expect that a signal OCE is for Port B ( OCE = Ouput Chip Enable?)
But where is write signal for port A?

Does anyone use Gowin FPGA and  could give a hint ?

Regards,
up8051

[mon2]

Hi.

1) the Tang Nano is fitted with the GW1N-1-LV - please note this p/n.

2) Section 3.3 details the attached document contains timing charts for this specific interface. Port A is for write data; Port B is for read data. Each port operates without the r/w signal.

[up8051]

Thank you.
The document was very helpful, the problem has been solved.

I have another question.
I have left about 400 LUTs , 2 BRAM blocks and  all User Flash. I would like to implement some simple softcore CPU to operate the buttons and the display.
Can you recommend something simple and proven?

[nctnico]

One of the Picoblaze portable clones might work: https://en.wikipedia.org/wiki/PicoBlaze

[up8051]

pacoBlaze - last modification 14 years ago
copyBlaze - 5 years ago

Projects appear abandoned.

[Someone]

No updates doesn't mean its bad, can also mean its so good no one needs to change it.

Picoblaze kcpsm3 (4-lut era), 17 years?

[langwadt]

pacoBlaze - last modification 14 years ago
copyBlaze - 5 years ago

Projects appear abandoned.

or they were perfected long time ago and doesn't need anymore work

[mon2]

By no means would I consider myself a pro in this area but do not believe that 400 LUTS will be enough room to support a soft micro.

If practical, consider to source a Gowin device with the hard M3 CPU. They are not much more costly as Gowin has cut a deal with ARM for the IP. As per my past posts, highly recommend to contact Edge Electronics (USA) unless you have a solid contact in your region. The benefit of the hard M3 is that very few LUTS are used to enable and configure the CPU which leaves most of the logic for your other needs.

Alternatively, consider to implement away the desired functions with Verilog Coming from a C (Borland DOS) background, the Verilog learning has been fun to date.

A few great websites to recommend reading:

fpga4fun - learned a great deal from Jean's website and initially started with the RAM based Altera ACEX-1K device
nandland.com

It should be rather straightforward to sample GPIO pins for switch closures, etc. - just debounce the contacts as the FPGA will catch them.

What is your target display? Text or Graphics ? I2C or SPI based ?


Update:

Here is how to monitor a switch closure in Verilog:

https://www.fpga4student.com/2017/04/simple-debouncing-verilog-code-for.html

[up8051]

Simple info about my Project:
- language: VHDL
- hardware platform: Sipeed Tang Nano 1K
- input:  signals from pinball DMD  (Dot Matrix Display), Clock Data, Page Strobe
- output: VGA signals (H_Sync, V_Sync, 16bit color)

I would like to add small configuration menu to set: colors palette, VGA mode, position of the image on the screen  etc.

I am considering two options :
1. external uP (ATtiny)
2. soft-core

The first option is easier to implement, but the second one may be more interesting. I never use soft-core.
Tang Nano 4K is too expensive for this project.

[nctnico]

pacoBlaze - last modification 14 years ago
copyBlaze - 5 years ago

Projects appear abandoned.

or they were perfected long time ago and doesn't need anymore work

That is exactly the case! Sometimes a project is simply done. These are extremely simple programmable statemachines that don't have a lot of complexity in them. IIRC I have used Picoblaze for the first time 20 years ago which was already a mature design at that time.

[SiliconWizard]

I don't know how many LUTs a Picoblaze would take. But I know it's a pretty limited architecture that is terribly inefficient for most programming languages, except using directly assembly, or using Forth, from what I've seen.

As an alternative, I can suggest the LatticeMico8 : https://www.latticesemi.com/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores02/Mico8.aspx
It takes as few as ~200 LUTs on a MachXO2 (LUT4), so that should fit here. And IMO it's more usable than the Picoblaze if for instance you want to use C.
Source code is available (Verilog) along with a version of GCC that supports it as a target. The fact it's in Verilog is no problem, you can absolutely interface it with VHDL code. I have never used it on FPGAs other than Lattice's, though, so I don't know how much effort "porting it" (if there is any significant porting to do) would be.

These days, I would of course also have suggested a RISC-V core, but even the small PicoRV32 in the smallest configuration will take more than 400 LUTs.

Anyway, 400 LUTs - that's really not much. Even if you can fit a soft core (and the LatticeMico8 would), you'll need additional resources for interfacing it with the rest of you design and maybe add a couple peripherals to enable it to do anything useful, so that'll be kind of hard to fit.

[nctnico]

I don't know how many LUTs a Picoblaze would take. But I know it's a pretty limited architecture that is terribly inefficient for most programming languages, except using directly assembly, or using Forth, from what I've seen.

Don't even bother using anything else than assembler on the Picoblaze! Part of the fun when using the Picoblaze is determining whether to implement something in the Picoblaze software or in the FPGA. At some point I had to do something with samples using u-law compression. Instead of decompressing in software, I created a ulaw compressor / decompressor in the FPGA and all the Picoblaze had to do is move the data around.

Picoblaze needs only a handfull of LUTs. That is the whole purpose of it. IIRC it was tailored specifically to fit the LUTs in Xilinx Virtex2 / Spartan devices. The whole thing was coded by instantiating device specific primitives. The Gowin FPGA the OP uses is really really small and with what is leftover it will be hard to fit a core with more features.

[c64]

Another option, if you have some extra time, you can make your own cpu. You don't need many instructions and it can easily fit in 100-200 LUT. Registers can be stored in memory to save LUTs, like on MC6800. But you can only code in assembly

[up8051]

After changes to the main program, I have about free 650 LUTs .

I wouldn't like to use Verilog because I don't know it and making corrections can be confusing.
I will try to use Micro8 (because there are sources in VHDL) or pauloBlaze .

Gowin has IP for picoRV but only for larger FPGAs.

[gnuarm]

I have worked with my own soft core CPUs and looked at others.  I prefer the MISC style processor (Minimal Instruction Set Computer) which is pretty much a simple stack machine (also called NOSC for No Operand Set Computer).  I also program in assembly/Forth since they are very similar on a stack machine and you don't need fancy debugging tools. 

Here is a generic reference to a wide variety of soft core CPUs from the most simple to the most complex.  If you spend some time looking at this data (it's a LOT btw) you will find some things that blow your mind. 

https://opencores.org/projects/up_core_list/summary

https://opencores.org/projects/up_core_list/downloads

https://opencores.org/usercontent/doc/1523749899

There is a microBlaze that only uses 260 6LUTs in a kintex-7-3.  Yeah, he doesn't try to level the reporting, he just tells you what type of LUTs were used, 4 input, 6 input, A which I assume means Altera?

Even more interesting is the 320 6LUTs risc-v virtex-u-2 by Jan Gray that gets 1171.9 KIPS per LUT!  It is 1 clock per instruction and runs at up to 375 MHz.  Ohhh... it's proprietary, only in the list for reference...

If you are interested in the stack processors (labeled "Forth" in the tables) check out the J1 and J1a from James Bowman.  It is a simple design, 1 clock per instruction up to 400 MHz.  It is in Verilog, but I believe it has been translated to VHDL which is not hard even if you do it yourself.  Rather than worry with language issues, just look at what registers and logic the Verilog is describing and write that in VHDL.  It is most likely pretty straight forward code. 

Anyway, lots and lots of data to analyze there.  The guy's name is Jim Brakefield.  He must really love this stuff to do all this work.  He's been keeping this list for at least 10 years, probably longer.