Help on translate schematics to Verilog.

[caius]

Hi,
I need to translate into Verilog some KiCad schematics and came across the attached symbols.Is the first a tristate buffer and the latter two AND gates tied to a NOR gate?How to code them in Verilog (well, I use Quartus schematics for now...)?Thanks in advance

[ataradov]

Code: [Select]

wire out = ctrl ? ~in : 1'bz;
Keep in mind that in a likely scenario of an FPGA, this only works for I/O pins. There is no tri-state logic inside the fabric. For custom silicon it is possible to have tri-state logic, but it is not common.

Code: [Select]

wire out = ~((a & b) | (c & d));


[BrianHG]

https://www.eevblog.com/forum/projects/verilog-shift-register-question/msg5448701/#msg5448701

You may define a 'wire y' before my examples, or, change my 'assign' into a 'wire' as 'ataradov' illustrated above.

[caius]

Thanks for reply.Is the tristate buffer of my picture with inverted output?All other images on the net have no circle on the output (like the attached image, it's the Quartus primitive)

[Wiljan]

(well, I use Quartus schematics for now...)?

If you use Quartus and have made a schematic, then while the schematic are selected you can click "File"/"Create/Update"/"Create HDL Design File from current file" (the schematic)  select verilog, give it a name, quartus will then make a verilog version of your schematic.

[caius]

[

If you use Quartus and have made a schematic, then while the schematic are selected you can click "File"/"Create/Update"/"Create HDL Design File from current file" (the schematic)  select verilog, give it a name, quartus will then make a verilog version of your schematic.

Thanks, I did it.I have these other two KiCad symbols that I'm try to identify, are they a D flip flop and a D latch with enable?Not sure though.

[tggzzz]

Hi,
I need to translate into Verilog some KiCad schematics and came across the attached symbols.Is the first a tristate buffer and the latter two AND gates tied to a NOR gate?How to code them in Verilog (well, I use Quartus schematics for now...)?Thanks in advance

You should think in terms of "translating" the specification/function implemented by the schematics into the equivalent specification/function implemented in an FPGA.

Trying to translate gates means that - at best - you will end up with the same bugs. Normally you will also end up with a lot of irrelevant detritus which will slow the operation down and be space inefficient.

If you are familiar with software, think of your question as being how to translate an C statement into an ADA statement. The C statement is very permissive w.r.t. overflows, concurrency, valid values. Do you need top ensure the ADA statements preserve those properties?

[xvr]

> I have these other two KiCad symbols that I'm try to identify,

If you have KiCAD schematic file you can fetch type of symbol from it. Just open it in KiCAD, select symbol and press 'E'.

[caius]

> I have these other two KiCad symbols that I'm try to identify,

If you have KiCAD schematic file you can fetch type of symbol from it. Just open it in KiCAD, select symbol and press 'E'.

No, unfortunately I have a PDF of schematics but not the source.

[caius]

> I have these other two KiCad symbols that I'm try to identify,

If you have KiCAD schematic file you can fetch type of symbol from it. Just open it in KiCAD, select symbol and press 'E'.

Thanks for reply.I just need the Verilog modules of the two gates to be implemented as symbols in my Quartus schematics.No ned to be FPGA compliant (well, I'm going to use MAX7000S CPLDs)

[Wiljan]

[

If you use Quartus and have made a schematic, then while the schematic are selected you can click "File"/"Create/Update"/"Create HDL Design File from current file" (the schematic)  select verilog, give it a name, quartus will then make a verilog version of your schematic.

Thanks, I did it.I have these other two KiCad symbols that I'm try to identify, are they a D flip flop and a D latch with enable?Not sure though.

See the difference on the 2 flip-flops the one with clk will only change data on posedge of the clk the other will do as long enable are valid

[caius]

Thaks for replies to everyone, I was able to improve the design.But now I'm facing a timing issue, the FPGA does not like the external clock signal input very much.I had to use an external 3-state  buffer (74LS367) to fix this issue but it's not a convenient solution to add another IC to the design.How can I achieve the same result with Verilog?Thanks in advance.

[BrianHG]

Thaks for replies to everyone, I was able to improvedesign.But now I'm facing a timing issue, the FPGA does not like the external clock signal input very much.I had to use an external 3-state  buffer (74LS367) to fix this issue but it's not a convenient solution to add another IC to the design.How can I achieve the same result with Verilog?Thanks in advance.

Unless the clock signal is bouncing around, full of interference, this is not where your problem lies.  can you show us a scope shot of your clock signal?  You may just need proper termination or a 5pf cap at the end, or correct your PCB and ground plane.

I know how one may think I can just take an example wired TTL logic and code a FPGA WYSIWYG accordingly making the same function, but, this can be a flawed assumption.  Some logic designs just need a touch of re-thinking to properly code it as synchronous logic for the FPGA to prevent stability issues.  Also, for sloppy source signals, there are additional tricks to make your design noise immune.

[ataradov]

What exactly do you mean by FPGAs not liking the clock. This description is meaningless. What is the issue? And how did you use the buffer to fix it?

Also, what is the clock speed? Have you defined it in the constraints file?

[caius]

The clock speed is 8MHz.Here is signal that causes issue:



Her's is the same signal thru a buffer :



Here's is how I wired the 74LS367 :



About the issue, the hosting hardware where I'm tring the FPGA device is an old arcade board.When I use the original 8MHz clock I get sprites issue.If I use the buffered one the sprites are good.
I tried also the PLL of the FPGA (a MAX10) with no luck.In my design I routed this 8MHz clock (called 'HCLK' on the original schematics of the arcade PCB) to pin 27 of the MAX10 FPGA.My design is a replacement of a custom chip (a sprites generator) used on this arcade board.

[BrianHG]

Though sluggish, it looks ok.

You do realize that going through a logic gate delays your clock, right?

You also know that the max10, even the slowest one, runs it's logic something like 10x faster than the old 74LSxx ttl logic you are trying to replicate, right?

What does your logic look like?  Maybe it is not clock noise, but a logic delay which you require.  There are means of doing this inside the max10.

Did you know that on the max10, you can set IO slew rates and output drive currents for the IOs?

[xvr]

Your 'buffered' clock seems worse than original. And 74LS series is a VERY SLOW. It should not be used as clock buffer (and used at all on 8MHz, IMHO).

> When I use the original 8MHz clock I get sprites issue.If I use the buffered one the sprites are good.

Very likely that there is some problem with RTL.

[BrianHG]

Your 'buffered' clock seems worse than original. And 74LS series is a VERY SLOW. It should not be used as clock buffer (and used at all on 8MHz, IMHO).

> When I use the original 8MHz clock I get sprites issue.If I use the buffered one the sprites are good.

Very likely that there is some problem with RTL.

We do not know what his logic is doing.
If he is using the FPGA to drive data on a bus and it is replacing TTL logic, it could be a setup & hold issue where the FPGA responds so fast that the relevant data is removed too quick, or incoming clock data being latched too soon.

Remember, we are dealing with a beginner trying to replicate drawn 74LS ttl schematics.

I would say add 1 to 3 'LCELL' buffers for the clock input on the FPGA to replicate the external buffer delay.  Again, this is the wrong way to do things, but if it works, it illustrates a timing issue, not a noisy or weak signal issue.

Redoing the OPs code from a WYSIWYG code style to what the logic supposed to function like or inverting the clock at the right points in his code would probably help.  The other choice is to enable Quartus' WYSIWYG feature in their compiler setting window to ensure Quartus isn't optimizing out his code to a simpler faster design.

To achieve proper perfection, the OP would need to write a proper .sdc timing constraints file to replicate the actual timing of the TTL circuit he is trying to replace.  However, this is for the really advanced users.

[caius]

Though sluggish, it looks ok.

You do realize that going through a logic gate delays your clock, right?

Yes, I do.

You also know that the max10, even the slowest one, runs it's logic something like 10x faster than the old 74LSxx ttl logic you are trying to replicate, right?
Did you know that on the max10, you can set IO slew rates and output drive currents for the IOs?

Yes, I know.I made man other designs (mainly with MAX7000S CPLDs) and sometimes I fixed them by enabling the SLOW SLEW RATE option.But in this case I did not the trick.

What does your logic look like?  Maybe it is not clock noise, but a logic delay which you require.  There are means of doing this inside the max10.

I made the hardware part of this custom IC replacement, it runs Verilog code from someone else who decapped and tracesd the original custom IC.Perhaps I do need a logic delay.I tried other TTL (like inverters) but I  totall fixed the issue using a 74LS367 in the above configuration.How can I add logic delay inside the MAX10?As said, plaing with slew rate did not change anthing.Thanks.

[caius]

Your 'buffered' clock seems worse than original. And 74LS series is a VERY SLOW. It should not be used as clock buffer (and used at all on 8MHz, IMHO).

> When I use the original 8MHz clock I get sprites issue.If I use the buffered one the sprites are good.

Very likely that there is some problem with RTL.

We do not know what his logic is doing.
If he is using the FPGA to drive data on a bus and it is replacing TTL logic, it could be a setup & hold issue where the FPGA responds so fast that the relevant data is removed too quick, or incoming clock data being latched too soon.

Remember, we are dealing with a beginner trying to replicate drawn 74LS ttl schematics.

Well, like I said before, I'm trying to replace a custom IC with a FPGA solution that runs a Verilog code written by someone that decapped the IC, traced the cells, took schematics and, lastl, wrot Verilog.This replacement will run on an old arcade board made by man TTLs so, I think, there is some timing issue because the FPGA is too way fast for the hosting hardware

I would say add 1 to 3 'LCELL' buffers for the clock input on the FPGA to replicate the external buffer delay.  Again, this is the wrong way to do things, but if it works, it illustrates a timing issue, not a noisy or weak signal issue.

How to insert 'LCELL' buffers to the clock input?

Redoing the OPs code from a WYSIWYG code style to what the logic supposed to function like or inverting the clock at the right points in his code would probably help.  The other choice is to enable Quartus' WYSIWYG feature in their compiler setting window to ensure Quartus isn't optimizing out his code to a simpler faster design.

How to enable this WYSIWYG feature on Quartus?Sorry for all these questions but I'm tring to learn.

To achieve proper perfection, the OP would need to write a proper .sdc timing constraints file to replicate the actual timing of the TTL circuit he is trying to replace.  However, this is for the really advanced users.

This is another thing on my TO-DO list when (and if..) I get more skilled

[BrianHG]

The max10 is something like 4x faster than a Max7000.

For an added delay in the Max10, use an 'LCELL' primitive.

IE: 'clock input pin source net' - 'LCELL' - 'LCELL' - 'internal clock net for your code'

Every 1-3 LCELL will slow down the clock to the extent of a Max7000s internal delay.

Note that a slow slew rate on the Max10 is for changing an IO from ~400-500Mhz to ~100-150Mhz.  It is not like the Max7000 slow slew rate designed for ~30-60MHz instead of ~150Mhz.

[BrianHG]

How to call a LCELL:\
https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/mapIdTopics/jka1465580081388.htm

Simple enough... (do not use it to feed a PLL clock input, yours supposed to use the PLL output phase controls to do this correctly, the LCELL is a delay trick for delaying a signal by ~4ns.)

For WYSIWYG - Stands for 'What You See Is What You Get', this is how it changes Quartus:
https://www.intel.com/content/www/us/en/docs/programmable/683641/21-3/wysiwyg-primitive-resynthesis.html

This feature tries to undo the 74LSxxx photocopied design and tries to make a true synchronous output.  IE: makes your poor code run faster and more parallel.  It may be doing the opposite of what you need.

See attached photo for where you see it in the options...

[xvr]

> I made the hardware part of this custom IC replacement, it runs Verilog code from someone else who decapped and tracesd the original custom IC.

Take a close look at Verilog code (or original schematic). Direct replacement or 74LS style logic (even packed inside custom IC) would not work on FPGA.
FPGA design process expect to deal with synchronous schemes. Design from separate 74 series logic often is not synchronous. And it will work in original form (in discrete ICs) because small transient glitches from logic absorbed by internal delays in logic and/or capacity of nets, before feeding to clock inputs for another IC. With FPGA it will not work, all glitches directly passed to clock inputs and spoil everything.

FPGA design should be fully synchronous - all clock input all of D triggers and/or latches should be directly connected to input global clock.

> I tried other TTL (like inverters) but I  totall fixed the issue using a 74LS367 in the above configuration.

It is not a fix. You reduce slew rate of clock raise/fail. The same effect you can archive by adding small capacitor in parallel in clock pin of MAX (and a small series resistor before capacitor).
BrainHG is right - your issue looks like signal-to-clock setup or hold (or both) issue.

Again, this is the wrong way to do things, but if it works, it illustrates a timing issue, not a noisy or weak signal issue.

Exactly

[BrianHG]

WYSIWYG compiler setting location:

[caius]

Tried the WYSIWYG option with no luck.
I attach the schematics and Verilog implementation if someone want to check them.

P.S:
The original custom chip has also a couple of RAM blocks inside (they have been implmented in Verilog with registers as you can see from code)

P.P.S.

Does the smalll capacitor must be installed between clock input and GROUND?Often on arcade boards I can see this kind of fix using 100 pF cercamic capacitors (especially on clock input of counters).