Your 'buffered' clock seems worse than original. And 74LS series is a VERY SLOW. It should not be used as clock buffer (and used at all on 8MHz, IMHO).
> When I use the original 8MHz clock I get sprites issue.If I use the buffered one the sprites are good.
Very likely that there is some problem with RTL.
We do not know what his logic is doing.
If he is using the FPGA to drive data on a bus and it is replacing TTL logic, it could be a setup & hold issue where the FPGA responds so fast that the relevant data is removed too quick, or incoming clock data being latched too soon.
Remember, we are dealing with a beginner trying to replicate drawn 74LS ttl schematics.
I would say add 1 to 3 'LCELL' buffers for the clock input on the FPGA to replicate the external buffer delay. Again, this is the wrong way to do things, but if it works, it illustrates a timing issue, not a noisy or weak signal issue.
Redoing the OPs code from a WYSIWYG code style to what the logic supposed to function like or inverting the clock at the right points in his code would probably help. The other choice is to enable Quartus' WYSIWYG feature in their compiler setting window to ensure Quartus isn't optimizing out his code to a simpler faster design.
To achieve proper perfection, the OP would need to write a proper .sdc timing constraints file to replicate the actual timing of the TTL circuit he is trying to replace. However, this is for the really advanced users.