Help with this verilog video

[lawrence11]

Lecture 2 of 10.

Here in this @ 5:10 , the line that bugs me is WORD [i+3:i], because it has an error box that points to it

Mr Kirk Weedman says its in the same direction? So its good or not, or did he just make a mistake? he never states this is a error but the box is there.

[ataradov]

The error is because index is not constant.

This construction would be fine in the 'generate' block. Because in the end it still results in a fixed index.

[langwadt]

it's right on the slide: indexes must be constants

[BrianHG]

That one got me thinking, didn't I successfully use variables in my indexes in the past?

I just checked, and it was not a normal variable, but a 'Parameter'.

If you want parameters for your Verilog module, say a configuration for the address size for a block of memory, the assigned label you use for the parameter is allowed in your indexes.

[ejeffrey]

Yes, parameter and `define values are constant so they can be used freely in index expressions.

You can use a single variable expression index with no problem. Only for ranges are constant expressions required.  Note that you can also do a variable range select using the -: syntax:  myreg[8*i + 7 -: 8] will select bytes out of a multi-byte register.  The starting index can be variable only the offset has to be constant.

[kfnight]

The desire for non-constant width part selects has been on the SV ballot for a while now. See https://accellera.mantishub.io/view.php?id=2684

[SiliconWizard]

Note that it's been available in VHDL for ages.