A lot of applications don't need the speed, including most of mine. We don't need any of the fancy interfaces, just a lot of low power logic.
That's a very niche use case, and the one that wouldn't look good in marketing ("We just released a brand new FPGA which can't even do DDR2 - not to mention DDR3/DDR4 or super-fancy LPDDR4, but it's got LOGIC!"
). Nobody is going to take seriously an FPGA with considerable amount of logic which can't even talk to DRAM nowadays, so a vendor would have to add some memory inside the package to compensate for meager IO abilities, which would drive up cost. The reality is IO needs of FPGA design usually are proportional to the amount of logic resources, hence why devices with lots of logic tend to be in a big BGA packages with lots of balls.
I'm not saying your usecase does not exist or is invalid somehow, I'm just telling you how FPGA vendors themselves explain why no modern FPGAs are released in anything but BGA packages (I asked that quesion to Xilinx engineers during one of webinars a few years back when they were introducing Spartan-7 devices which were initially announced in QFP package among others, but that was quietly dropped somewhere along the way and never saw the light of day), and even those tend to become smaller the more modern FPGAs are. Everybody want to make their products smaller and lighter - not bigger and heavier. And as a side effect of reducing size you also improve both power and signal integrity because shorter (or ideally non-existant in case of chip-scale packages) bond wires have both shorter impedance discontinuity (improving signal integrity) and less inductance (improving power integrity). This allows ever faster signals to still have enough loss margin to be useful.
The choice between QFP & BGA is not mine. However, I would highly suggest you don't try and assume and draw conclusions on why people need to use QFP over BGA. A lot of our boards have to use 2oz copper, which can be difficult for BGA soldering. We have a few extremely experienced hardware engineers who have told us BGA would be very difficult on such boards given our boards are also extremely cost sensitive.
This problem is typically solved by using modules - when you have a small hi-tech multilayer board with all high-speed stuff, and a low-tech carrier board with all that power stuff. Alternatively, instead of 2oz copper you can simply route the same net over multiple layers in parallel, achieving the same result as thicker copper - this is often used if you only need a few high-power traces. This is routinely done on a lot of FPGA and higher-end SoC boards - with ever shrinking Vccint voltages modern FPGAs and SoCs draw ever higher currents, so in order for all that current to be delivered to device and not lost along the way you have to have multiple power planes in parallel. As a side effect, such arrangement reduces inductance of a PDS which allows for a faster step response and thus better power/ground stability, also contributing to improving signal integrity because bouncing ground/power rails make for bad reference planes.
As for the cost - BGA typically allow making boards much smaller than any other package, and a size is a big driver of price - because not only bigger PCB cost more to manufacture, it also requires bigger enclosure, which also cost more as material cost is the primary cost factor when we're talking about production volume.
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Topic: I'd like to know your experience with Gowin FPGAs (Read 7292 times)
