Hi, all!
We intend to use Lattice iCE40 UltraPlus series (ice40up5k exactly) in our low-power consumption application. We use a serial DDR external RAM (Double-Data-Rate). But I can't find if iCE40 Series support special DDR primitives like ODDR in Xilinx. Could anyone have experience?
If iCE40UltraPlus does not support DDR primitives, the only way is to use a 2x clock frequency to operate. I sincerely get help from here.
Best regards.
I don't think they do. Haven't seen any mention of that in the datasheet nor in other docs.
And keep in mind these are cool, but relatively "slow" devices. I/O buffers are rated 250MHz max. (Above 2.5V for outputs, less otherwise.)
So if you're hand-implementing DDR, your data rate may be much lower than you'd otherwise expect from DDR RAM. That said, its logic blocks wouldn't take high enough Fmax for it to make a difference anyway.
Using DDR RAM with an iCE40UP sounds a bit odd - what's your use case?
To be honest, the motivation we chose iCE40UltraPlus is its low-power-consumption feature. We have a project powered by single core optical fiber, and a photovoltaic cell is used to convert light to electricity. Considering the ultra low power consumption of iCE40, our team leader made the ultimate decision and he allocated this job to me. ice40up5k only has 48 IO pins, including power and ground, literally the general input/output ports are less, so the hardware engineer connected a DDR SPI RAM to it with only 4 pins used. (CS, SCLK, MISO, MOSI)
but the SCLK is Double-Data-Rate, the first time I see DDR SPI.
In conclusion, if Lattice does not offer DDR primitives, I tend to use two clock domains in my design, clockA for general use, clockA*2 for operating DDR SPI.
Or option 3: just use the SPI in Single Data Rate (SDR) mode. If that’s fast enough…
it's a quite brilliant idea, sir. thanks for your reply.
my colleague, the hardware engineer dude created troubles, haha, but for us, we solve troubles.
if I force DDR SPI working in SDR SPI, I only concern about the data on rising edge, and ignore the falling edge, that needs a little trick.
@(posedge clk) for controls, @(negedge clk) for reading back data, though you need to latch that data through a second adjacent @(posedge clk) to sync the data to your master system clock. Depending on the fpga's speed and clock frequency, it can work just fine as a d-latch to another d-latch with 0 logic in between can potentially run at 100mhz or more. IE, it would be as if you had a 200mhz primary clock running in sdr mode. But, how good will your .sdc file be and how good will lattice's IDE handle it. I know with Altera Quartus, even with their old PLDs, this wouldn't be a problem and the compiler would spit out any timing issues during timing analysis. Lattice on the other hand??? If you are using Lattice Diamond, they have recently removed .sdc file support for their own custom timing constraints architecture. I wasn't impressed.
Looking at the IO buffer diagram you can see that there are DDR structures for both inputs and outputs.
I have used these on the ICE parts and they work fine.
However, I found the PLL to be more limiting in many cases compared to let's say a MACH-XO3 device.
Also, as others have said these parts are pretty slow. Don't expect your main clock speed to be much higher than 60 MHz.