Implementing USB controller IP on FPGA

[stud.mk]

Hi all,

I’m currently exploring a project idea related to implementing a USB host/controller IP on FPGA, and I was hoping to get some guidance before diving in.

I’ve gone through the EHCI/xHCI specifications at a high level and was considering using a low-pin-count USB PHY/interface module, with the goal of building a basic USB controller IP (primarily for learning and experimentation).

Before starting implementation, I wanted to ask:

Are there any recommended approaches, references, or prior implementations I should look at?

Has anyone here attempted a similar USB controller design on FPGA(host)?

I also came across USB interface/controller modules such as TSUSB/TSUB-series devices from Texas Instruments, and I’m trying to understand:

Which external USB interface/module is easier to work with from an FPGA point of view?

Has anyone here used or implemented support for such modules, or can recommend an alternative that’s more FPGA-friendly?

Any suggestions, links, or experiences would be really helpful before I commit to a specific approach.

Thanks in advance!

[Berni]

The way to do this is to simply build a reasonably fast softcore CPU inside the FPGA, use one that can run compiled C code fairly performant, find one of the bit banged USB Host implementations online and port that into your softcore CPU.

During the porting process you will find what kind of peripheral logic fits best for talking to the outside world for your particular piece of code you decided to port. This will most likely be some sort of shift register (perhaps fed by a FIFO) and some simple state logic controlled by flags.

If you want to go fast with 480Mbit or 5Gbit USB then you might need to build some more complex logic that handles the USB port, so that it is more self sufficient to free up the softcore CPU from having to hit strict timing requirements. To hit 5Gbit you will also need a fancy FPGA with dedicated serdes blocks.

[rteodor]

To hit 5Gbit you will also need a fancy FPGA with dedicated serdes blocks.

FPGA n00b here, asking dumb questions: is GateMate considered fancy ?

[Berni]

FPGA n00b here, asking dumb questions: is GateMate considered fancy ?

Well it does have 5Gbit SERDES modules so it should be capable of it. Not the fastest serdes out there but fast enough for USB 3.0. Tho it is a pretty new FPGA vendor so it is to be seen how good the software support is.

The SERDES modules have long been regarded as a premium feature on FPGAs. The chips with it are not that much more difficult to produce but they give the FPGA capability to talk to things that it otherwise wouldn't be fast enough to talk to. So because you need this feature to talk high speed the FPGA vendors tended to price these FPGAs at 2x to 5x the price as compared to the same FPGA without serdes, just because they know you are forced to buy one with it if you want to go fast. But yeah id imagine a considerable amount of R&D went into designing these serdes blocks (especially the really fast >20GBit ones) while a lot of customers don't need it.

[stud.mk]

Thanks, that makes sense.

Starting with a softcore CPU running C and porting an existing bit-banged USB implementation seems like the right approach, especially for low-/full-speed USB given the board constraints.

If you know of any reference designs or open-source repositories that implement USB host controller logic in Verilog/VHDL, pointers would be appreciated.

Thank you.