JTAG: Tips for making it work?

[obiwanjacobi]

Hi,

I am trying to bring up my homebrew frankenstein retro board with a XC95288XL CPLD on it.
Here is the schematic: https://github.com/obiwanjacobi/zalt2/blob/main/Main%20Board%20v2.0/Schematic.pdf
(The project is on github so look around if you want to know more)

I have a Xilinx USB Cable II programmer and use ISE Webpack software to program the device.
However the programmer (iMPACT) keeps reporting errors, like finding a lot of unknown devices during the boundary scan.

Trying to debug this I found out that I messed up the connector (J3) where I should have swapped TDO and TDI*.
Using individual dupont wires between programmer and board fixes that, swapping these signals.

I have checked that my hand-soldered 144-pin package was attached okay by beeping-out between the header pins and the (top of the) CPLD pins - not on the PCB pads.
I have checked I have 3V3 on the chip (all VCCINT and VCCIO pins) and GND is good.

I noticed the chip is getting slightly warm when I apply power and am a bit concerned by that.
The XC95288XL part was purchased on AliExpress - so I half expect it to be a fake... 

Q: So what other things can I try?

*) Turns out I had not messed up and the TDO/TDI must not be swapped.

[nctnico]

I'd make sure the grounding between the JTAG adapter and your board is solid. Also power the board from a non-switching bench PSU. Not some AC/DC switching adapter with half the mains voltage at the output.

[xvr]

I noticed the chip is getting slightly warm when I apply power and am a bit concerned by that.

XC95 series is a power hungry beast, so it's normal

[obiwanjacobi]

I'd make sure the grounding between the JTAG adapter and your board is solid. Also power the board from a non-switching bench PSU. Not some AC/DC switching adapter with half the mains voltage at the output.

I use a PC PSU.... 
I have several (3) dupont wires that connect GND between the programmer and the board.

In the meantime I have:
- slowed the programmer to 750kHz (lowest option)
- looked at the signals with a logic analyzer. I see activity but I don't know the JTAG (wire) protocol enough to make sense of it.
  For instance, I see some clock bursts but no response from the device (I would expect)...

I have ordered a 144-pin adapter board which I plan to use to solder a XC95288XL on and just test the JTAG in isolation... (I have a total of 5 chips)

[nctnico]

Do you have an oscilloscope? If so, please use that for these kinds of problems. A logic analyser hides way too much details. You probably have some signal integrity problem and only an oscilloscope can show that. I've seen people messing around with a logic analyser for two weeks without solving a similar problem you have. Using an oscilloscope showed the exact cause of the problem within 2 minutes.

[obiwanjacobi]

Do you have an oscilloscope?

Yes, a simple one channel hand-held.

What am I looking for?

[nctnico]

Using a single channel scope is going to be hard as it doesn't allow to investigate relationships between signals. But you can check the signals for edges (should have faster rise / fall times compared to the clock frequency) and the high / low levels must be good. If a signal is stuck half way, then there is something wrong. Maybe two outputs driving the same signal or a pull-up / pull down resistor with a value which is too low. Your first goal should be to have Impact scanning the chain and finding the FPGA correctly.

[obiwanjacobi]

I went over my schematic again - checking my assumptions.

1) Turns out that I was confused about the JTAG connection between the programmer and board/device.
I know you can chain multiple JTAG devices on a board (TDO=>TDI) so "naturally" I thought that is how you hook up the programmer too.
It turns out that all the JTAG programmer signals go to their corresponding board counter-parts.
"Everybody" (YT vids, blog posts etc) is really vague about how to actually hook it up.

2) I never realized there was a datasheet for the programmer. I found it yesterday and read about the PGND pin.
I had 'assumed' it was some sort of programmer-GND but its not. Its a Pseudo-GND.
I don't fully understand its function or use but it looked like it is controlled by the programmer.
And I had it connected to GND on my JTAG board header...

After disconnecting the PGND from GND stuff started working (I had to find the overwrite write-protect option):
Boundary-scan, identification, erase, read-back, verify... not 

When I program it, the program step succeeds but the verify step fails.
I don't know why. I can see it switches to what looks like SPI-mode..
After programming I read-back the .jed file and did a quick comparison and could not find any obvious differences.

So for now I will call this good. At least I can now continue to program something simple in the CPLD I can use to test the board with further.

Special thanks to @nctnico for his assistance.