lockup latch issue

[promach]

1. In https://vlsiuniverse.blogspot.com/2013/06/lockup-latches-soul-mate-of-scan-based.html , I am bit confused with the hold check and setup check waveform inside Figure 7

2. In https://www.design-reuse.com/articles/37956/lockup-elements-the-timing-perspective.html , how does lockup latch solve hold timing issue in Figures 1, 2 and 3 ? Note: I was reading in one other edaboard thread that says lockup latch adds a half clock cycle to the hold timing check path ?

[dtodorov]

I did not get into the corner details of the articles, but I think this latch insertion is needed only for SCAN operations (e.g. during ATPG vectro scan-in/out). In such scan modes, the flip-flops are daisy-chained into a large shift register-like structure (reffered to as scan chain).
Each scan FF has an input mux selecting normal data (comming from combo logic) or the output of the previous scan FF in scan mode.

The problem is, that during scan mode, the test clock (which clocks the scan chain) is common, and this means timing paths now exist between domains which probably are irrelevant in normal (not scan) operation of the logic.  These paths are likely to create setup/hold violations and tools will try to add balancing clock buffers, for instance.

From what I understand, this article suggests that a latch is used instead to architecturally avoid timing path optimization.