Looking for Easy-ABEL v4.x documentation (PAL, GAL)

[marcopolo]

Hi,

Does anyone have a copy of EZ-ABEL v4.x documentation?

Software available here: https://vetusware.com/download/ABEL%204/?id=13430

Thanks,
Marc

[marcopolo]

FYI, I tested this software with PAL20X10A et PALCE22V20 (used on a real board, not simulation), it work's fine 

[NivagSwerdna]

I seem to have a design despite having only read selective pages of the documentation!

One thing that I don't quite understand is why some of my outputs end up being negated but for some bizarre reason it has come up with a combination that actually works in my circumstances.

I tinkered with istype 'pos' and 'neg' but the behaviour seems to stay the same.  I should probably read some additional pages one day.

[marcopolo]

The documents I found about ABEL are here: http://marc.retronik.fr/PLD-FPGA/ABEL/

A useful book: Digital design using ABEL
Syntax from examples like ADDRESS = [A15..A12] is not supported by EZ-ABEL 4.30 but ADDRESS = [A15, A14, A13, A12] is OK

If you find other documents, tell me and I will add them.

[NivagSwerdna]

I managed to get my design done with very little effort. (It was only combinatorial)

I found...

Code: [Select]

To maintain the correct pin behavior, using detailed equations, one additional
language element is required: a ‘buffer’ attribute (or its complement, an ‘invert’
attribute). The ‘buffer’ attribute ensures that the final implementation in a device has
no inversion between the specified D-type flip-flop and the output pin associated with
Q1. For example, add the following to the declarations section:
Q1 pin istype ‘buffer’;
https://www.eit.lth.se/fileadmin/eit/courses/edi021/PDF_files/lattice/abel_design_manual.pdf

It's funny how all those things you learnt at college.... e.g. product terms.... seem to be accessible from the deep recesses of your brain when you need them.   ABEL seems simple and appropriate... I really should have made a bit more effort and tried VHDL but I'll save that for another day.

[marcopolo]

Thanks for the information.

I added here your pdf (without the 35 pages about ispDesignExpert):
http://marc.retronik.fr/PLD-FPGA/ABEL/LATTICE_ABEL_Design_Manual.pdf

I don't think VHDL is appropriate for simple designs with PAL or GAL.

Marc