MCU with FPGA vs. SoC FPGA

[DiTBho]

Even the brand new RaspPi 5 SoC only has a single PCIE2 line!

well, so imagine when you have a single PCI bus 32bit/5V, exported as "ISA bus", with a bandwidth of 5Mbyte/sec, then "voltage level adapted" to 3.3V. That's what you get with several cheap PCI to fpga development boards!

oh, and cheap means > 90 euro

[asmi]

well, so imagine when you have a single PCI bus 32bit/5V, exported as "ISA bus", with a bandwidth of 5Mbyte/sec, then "voltage level adapted" to 3.3V. That's what you get with several cheap PCI to fpga development boards!

oh, and cheap means > 90 euro

Sorry, but I live in 2023, not 1993.

[DiTBho]

well, so imagine when you have a single PCI bus 32bit/5V, exported as "ISA bus", with a bandwidth of 5Mbyte/sec, then "voltage level adapted" to 3.3V. That's what you get with several cheap PCI to fpga development boards!

oh, and cheap means > 90 euro

Sorry, but I live in 2023, not 1993.

The board was designed in ~2008, commercialized since 2010.

[asmi]

The board was designed in ~2008, commercialized since 2010.

It doesn't matter now, in 2023.

[DiTBho]

my two OW-boards are based on Mediatek SoC, designed in 2019, they are premium SBCs (150 euro each), they only have two miniPCIe slots, one is shared with the sATA lane, and it's mutually exclusive, either you use mini PCI, or you use sATA lane, you can't have both.

Another (cheaper, ~60 euro) example? the RBM33G, designed in December 2017, it has three miniPCIe lanes, two miniPCIe slots and M.2 slot, but that's because it's a router!

In my opinion it's already a good thing that the RPI-v5 has an exported PCIe lane, and it's a great thing, with which you can widely do great things.

(and by the way what do you have to do with much more bandwidth?)

[langwadt]

my two OW-boards are based on Mediatek SoC, designed in 2019, they are premium SBCs (150 euro each), they only have two miniPCIe slots, one is shared with the sATA lane, and it's mutually exclusive, either you use mini PCI, or you use sATA lane, you can't have both.

Another (cheaper, ~60 euro) example? the RBM33G, designed in December 2017, it has three miniPCIe lanes, two miniPCIe slots and M.2 slot, but that's because it's a router!

In my opinion it's already a good thing that the RPI-v5 has an exported PCIe lane, and it's a great thing, with which you can widely do great things.

(and by the way what do you have to do with much more bandwidth?)

yeh, a lane of PCIe gen 2.0 is ~500MB/s and afaiu the rpi5 is capable of doubling that forcing the (unsupported) Gen 3.0

[asmi]

they are premium SBCs (150 euro each)

In my opinion it's already a good thing that the RPI-v5 has an exported PCIe lane, and it's a great thing, with which you can widely do great things.

And there are many great things which you can not do...

(and by the way what do you have to do with much more bandwidth?)

Video processing. PCIE2x1 is not enough even for 1080p@60. But that is just one example, there are more - high-speed ADCs/DAC comes to my mind.

[DiTBho]

they are premium SBCs (150 euro each)

why are you laughing? it is not a SBC that is purchased in bulk by the mass precisely because it has a lot of things that common users (usually of the RPIs&C) do not need, and the two miniPCI slots are declared "premium" compared to the version without miniPCI slot, which costs a lot Less.

I don't see what's funny about it, but if you assume that "premium" means "industrial level", then we don't understand each other.

high-speed ADCs/DAC comes to my mind.

great point, here 

[gnuarm]

Thanks for your input, it's greatly appreciated.

The option of having additional 'front-end' MCUs, feeding into the larger, more capable MCU is actually quite an interesting one.

Or you can do the opposite, putting the entire design in a single FPGA. 

Most people don't think of using fpgas because they are so used to the sequential mindset of CPUs.  They forget that fpgas can do all the same things.

If you need something more complex than you are willing to roll on your own, like an Ethernet interface, then plop down a small MCU with Ethernet. 

[bitslip]

Even though OP had indicated using Zynq, I'm going to put another vote for a softcore processor + your logic, even if it's a Zynq physical devices.  The Vex-RISC-V open-source RISC-V softcore processor looks ideal, but Microblaze (the 32b one, MIPS-based) is pretty easy to work with.  The 64b Microblaze was really only introduced to enable addressing memory > 4GB, and yes, it's basically a beta design.

Be warned, you'll likely end up fighting the FPGA tools and Xilinx's weird ideas about how they should work vs. either writing code for the Zynq and/or creating your actual design

I also suggest using Vivado 2018, maybe Vivado 2019, all the newer versions have muddled the flow from "front-end" schematics to the software IDE because Xilinx is chasing other goals.  I don't think these version of Vivado are "perfect" (far from it) but the basics work.  You can embedd a Microblaze into a part and have "Hello World" running on it in less than 20 mins.