Newbie ModelSim question

[rea5245]

I'm just starting out with Verilog and using the free ModelSim that comes with Lattice iCEcube. Please forgive the total newbieness of this question.

How can I interact with a running simulation? I see there's a Wave window showing waveforms, and I can go through menus and dialogs to Force a wire to a certain value. But is there anything like a GUI where I set up a button that changes the value of a wire, or an "LED" that shows the value of a wire, or (I'm really pushing my luck here) an Edit box where I can type a character and it simulates a UART signal?

[BrianHG]

Though it is possible to edit / force a register's value or input's value and continue to run the simulation for x# of time, when using any simulator like Modelsim, usually you write a test-bench or ***_tb.v code.

Your inputs you wish to drive are usually written into the ***_tb.v source code which instantiates your main ****.v code you are working on.

Here are 2 simple Modelsim example source codes I have created which generate an initial reset pulse and system clock for testing my main code.  The instructions on how to run them in Modelsim is included as well as example setup_xxx.do script files which you can learn from.

https://github.com/BrianHGinc/Verilog-Floating-Point-Clock-Divider  (Only generates a system clock)
https://github.com/BrianHGinc/BHG_I2C_init_RS232_debugger  (Generates a reset and system clock)

My other far more advanced modelsim example which sends bus commands to an old 8 bit programmable sound generator.
https://github.com/BrianHGinc/YM2149_PSG_system
Here, the setup_psg.do / run_psg.do will run my 'YM2149_PSG_system_tb.sv' which has a trick to sending buss controls from arrays.

All my source code projects are fully documented with instructions in their .v or .sv code.
I recommend reading through the ***_tb.v files.

My advanced projects like: https://github.com/BrianHGinc/SystemVerilog-TestBench-BPM-picture-generator
Demonstrate reading and writing ascii files, like those from spreadsheets, to drive controls for my verilog source code and also demonstrate writing binary generated .bmp photos.  This is only for when you really need to go advanced.

[BrianHG]

Just so we are clear, in your test bench source file, you can write:

Code: [Select]

initial begin

clk = 1 ; // set clock to 1
rst = 1; // set rst to 1
#(10) ; // wait 10ns or 10ps...

clk = 0 ; // set clock to 0
rst = 1; // set rst to 1
#(10) ; // wait 10ns or 10ps...

clk = 1 ; // set clock to 1
rst = 0; // set rst to 0
#(10) ; // wait 10ns or 10ps...

clk = 0 ; // set clock to 0
wr_data = 200;
wr_ena = 1;
#(10) ; // wait 10ns or 10ps...

clk = 1 ; // set clock to 1
#(10) ; // wait 10ns or 10ps...

clk = 0 ; // set clock to 0
wr_data = 0;
wr_ena = 0;
#(10) ; // wait 10ns or 10ps...

end
This will just run the above script in order every time you restart your simulation.

In my github example codes, I use 'always' to generate a contineous clock and would not specify the 'clk = x' lines as seen above.

If you want to make a rs232 stream, just instantiate one of my 'sync_rs232_uart.v' in your testbench and feed it's input a byte and take it's output to feed the HDL code you are working on.