NovaGPU TS1T – Complete GPU in Verilog RTL: token dataflow architecture

[novastudios-hw]

I've been working on a complete GPU architecture implemented
in synthesizable Verilog RTL. Not a soft-core, not an emulator
— a full graphics pipeline designed from first principles.

The core execution model is called N.E.O.N. (Native Execution
Optimized Nucleus), a token dataflow architecture. Instead of
a traditional scheduler dispatching instructions to cores that
wait for data, N.E.O.N. lets the data itself trigger execution.
When a token arrives at a processing unit with both operands
ready, execution fires automatically. No warp scheduler, no
idle cycles waiting for operands. The Token Matching Unit (TMU)
handles this with 2-way set-associative matching and
match-and-fire logic.

The full pipeline includes:
- PCIe 4.0 x8 interface
- Token Matching Unit (TMU)
- Shader Cluster with custom 8-opcode ISA
- Three Tracing Unit (TTU) — hardware BVH traversal with
  AABB intersection
- Budget Controller — limits ray tracing to 25% of frame
  budget to protect rasterization performance
- Triangle Rasterizer — Pineda edge functions,
  perspective-correct barycentric interpolation
- Motion Vector Unit (MVU) — hardware frame generation
  without AI
- Dual-port SRAM with 64 banks
- AFA — hardware accelerator for water and vegetation
  animation using precomputed LUTs
- GIA — predictive frustum culling and BVH pre-update
  based on motion history
- MPE — prefetch predictor for SRAM access patterns
- PVA — post-processing on 8x8 tiles (AA, depth of field,
  gamma correction)
- Nexus — interconnect and arbitration layer

Current state:
- 14 RTL modules complete
- Synthesis and place & route successful
- 47/48 tests passing (97.9% coverage)
- 3D cube and tetrahedron animations generated directly
  from RTL simulation, exported as MP4
- One remaining bug: degenerate triangle edge case (A5),
  fix already identified

The long-term target is a 28nm MPW tapeout after FPGA
validation on a Tang Nano K9. Performance projections in
the whitepaper are analytical models, not measured silicon
— they're the targets that justify the architecture.

Being honest about what this is: a first-generation
validation device. The goal is to prove the technologies
work in real silicon before scaling up.

Full RTL source, testbenches, whitepaper, and build
instructions available. MIT license.

Repository: https://github.com/nova-studios-hw/novagpu-ts1t

For a deeper technical breakdown of the architecture,
execution model, performance projections, and roadmap,
a full whitepaper is available in the repository:

https://github.com/nova-studios-hw/novagpu-ts1t/blob/main/WHITEPAPER.md

It covers in detail:
- N.E.O.N. token dataflow execution model
- Per-module architecture breakdown
- Analytical performance projections vs traditional
  GPU architectures
- Memory subsystem design and SRAM strategy
- Roadmap from FPGA validation to 28nm tapeout

[ali_asadzadeh]

Thanks for sharing