Reason for Synopsys Synplify, MG Precision when Quartus/Vivado are free

[TheGreatNed]

Hi,

What advantage do Synplify or Precision bring to engineers when Quartus and Vivado are free? Do these programs synthesize the RTL 'better' than Quartus/Vivado (more efficient gate usage)?

Or am I missing the purpose of these softwares.

Thank you

[filssavi]

It has more to do with verification,
Vivado picked up coverage and UVM only very recently, while a lot of features (like formal verification are still missing
I’m not as familiar with quartus and modelsim intel edition but it is either the same or even worse (don’t be fooled by the modelsim name, the intel version is heavily cut down feature wise)

Also those tools are monolithic and GUI first, while they can be run headless through TCL (ugh) it often takes several dozen seconds to start everything
 up, making them unusable in continuous integration systems

Probably there are all sort of other differences, for example high end tools are able to automatically generate compliance reports for a while host of standards and certification bodies (think stuff like iso 26262 and similar)

Bottom of the line it is all stuff that is pretty useless to a single individual but very valuable to a big organisation
(ie. to set up and maintain a CI system properly is a job on it’s own, and with a single developer it usually ends up wasting more time than just running test manually

[SiliconWizard]

Note that whereas Xilinx doesn't seem to embed Synplify in their free tools, some other vendors do. Lattice, for instance, offers both Synplify Pro and their own tool (LSE) in Diamond for free.

Synplify tends to do a better job at synthesizing and optimizing overall, but vendor-specific synthesis tools OTOH, tend to synthesize in ways more adapted to the exact FPGA structure, so your results will vary according to your design.

Synplify can be used stand-alone too, whereas vendor-specific tools usually can't. Interesting when you need to fine-tune and really understand how your design is synthesized, and yes as said above, at some companies it can be a benefit too because they may already use others tools linked to Synplify.

Another point is that once you're familiar with tools like Synplify, you can more easily switch to designing ICs, as it's closer to what's used to synthesize the digital parts of ICs.

Not advertising whatsoever, but if you want to take a look: https://www.synopsys.com/implementation-and-signoff/fpga-based-design/synplify-pro.html

[filssavi]

Synplify tends to do a better job at synthesizing and optimizing overall, but vendor-specific synthesis tools OTOH, tend to synthesize in ways more adapted to the exact FPGA structure, so your results will vary according to your design.

Yea I can confirm, for a design, a fancy modulator and a simple(ish) serial comm protocol on a lattice ICE40 I started out using Synplify (due to my using SV), however I had to switch to lattice lse which is verilog only, (fortunately I wasn’t too invested in sysV but for few quality of life features Such as interfaces and 2D busses ) since i could not for the life of me achieve timing closure with that synthesizer.

The usage was similar between the two, maybe a tiny bit better on synopsis however nothing really to write home about

[miken]

With Synplify you can do something fairly nasty like c <= a / b, follow it with a bunch of pipeline registers, and the tool will magically spread the logic through the pipeline. Vivado is not capable of such feats, but you pay a lot less for it.

[asmi]

Vivado is not capable of such feats, but you pay a lot less for it.

Yes it is capable of this, it's called retiming, and it's available in free version as well as paid.

[miken]

Vivado does have retiming, but it's not as magically effective as Synplify's. In Vivado I often find myself having to push things around by hand.