Dev boards for FPGAs are a lot less important than one might think.
When doing MCUs of Linux SoCs you always test your stuff on real hardware, hence having a dev board is vital for doing anything. However in the FPGA world only a fraction of testing is performed on real hardware. The FPGAs are just so annoying to compile for and debug that most of the testing is performed within a simulator. Every major FPGA software package will include some form of HDL simulator that has specific support for that vendors chips.
So choose the vendor you like (Altera, Xilinx, Lattice..etc) since you will be forced to use their compiler, then grab a cheap board for their latest FPGA family in a decent sized chip (avoid the smallest chips they make, but don't buy any of the huge expensive chips). You mostly just need a board that has a bunch of LEDs, a few buttons and lots of IO pins brought out to a pin header. Some ports like VGA can be useful (FPGAs are good at video and is simple) but things like PS2 USB audio...etc are usually not useful.
Getting that LED blink on real hardware is certainly a good dopamine rush to motivate you to learn more, but as soon as your designs get bigger and more complicated, testing on real hardware becomes just an annoyance. Compiling the code might take 10 minutes then once you load it and run it, there is no 'debugger' to single step trough your code and look at state. You can't stop logic gates. The design runs at full speed all the time, all you can do is observe the IO pins. Hence every signal you want to see has to be brought out to a IO pin (another 10 minute compile) or routed to a logic analyzer implemented in FPGA logic (another 10 minute compile and eats a lot of FPGA resources). This is not fun when you are hunting down a nasty bug.
This is why HDL simulators exist. They are able to recompile just 1 changed source file in <1 second and also give you the ability to freeze the whole world at any point, letting you inspect every signal in the design at the click of a mouse. This makes iteration and fault finding much MUCH faster. Hence this is where HDL designers spend most of their time. This is very similar to the "test driven development" principle in software where you build modular code and slot each model into a test bench to exercise it and verify if its behavior is correct. This does mean you have to also write a test bench to simulate the rest of the system, but with the age of AI you can have the AI write most of that for you.
So before you buy it might be a good idea to just download the IDE from your preferred vendor and try to blink a IO line in a simulator. Once you buy a vendors chip you will be locked into using their IDE.