SATA Scrambling Algorithm

[Archy]

Encountered the following issue while implementing a SATA3 controller on an FPGA: the scrambling algorithm sometimes encodes data into primitives (ALIGN, EOF, etc.).

Setup:

1) Board: ZCU102.

2) Vivado 2019.2.

3) Transceiver configured via "UltraScale FPGAs Transceiver Wizard" with the preset "GTH: SATA (Pre-Production)".

4) All protocol layers (Command, Transport, Link) are custom implementations.

5) The controller is fully functional (initialization, read/write operations work without errors).

6) The scrambling algorithm was copied from outputlogic.com.

Issue Description:

During a write operation (DMA WRITE EXT command, 16 sectors of 512 bytes each), a 32-bit counter is written from 32'h8EF50800 (32'd2398423040) to 32'h8EF50FFF (32'd2398425087). However, at the 1524th word (value 32'h8EF50DF3 (32'd2398424563)), the data is scrambled into an ALIGN primitive (32'h7B4A4ABC). The scrambled data is then sent directly to the transceiver core. The drive does not report an error in response to this command, but when reading back the written data, a CRC error occurs. The ILA shows that the received data is "corrupted" starting exactly from the 1524th word.

Questions:

1) Am I correct in understanding that during reading, the transceiver core interprets the "encoded" ALIGN primitive not as data, causing desynchronization (after the 1524th word, I see garbage data)?

2) How can this behavior be avoided?


I attach .txt file with data sequences (the exact data being sent to the drive) with primitives and c++ program that generates this output in case someone is interested.

[iMo]

I've put your issue "as is" into the chatgpt (including the two files) and it proposed to me a new scramble_qword() function with several fixes in it..

[Archy]

This is my first time on this forum. Is it standard practice to send people to chatgpt in response to a problem, or are you racking up stats on replies to posts?

[Whales]

iMo: LLM's are very unreliable at solving problems, if you send someone to those then they'll be back with 10 problems.

Archy: if you do not get any good answers on this forum then I'd suggest an OS dev forum, there is a good likelihood you will find someone who has written SATA interface code in one of those.

[Langdon]

I'm sure some BSD or something has an open-source SATA controller.

[TomS_]

This is my first time on this forum. Is it standard practice to send people to chatgpt in response to a problem, or are you racking up stats on replies to posts?

I think for some people that is just the answer to everything.

Some of us don't use AI products, so dropping an answer like that with nothing further is practically useless.

[Langdon]

What about SATA 1 and 2?

I think SATA controllers are backwards-compatible.

What is your desired goal?

[asmi]

Is it standard practice to send people to chatgpt in response to a problem <...>?

Absolutely not. I personally think such responses are rude and ignore them.