Selecting pin impedance on fpga

[TeddyPython]

I'm trying to create a 50 ohm output from my altera cyclone iv e ep4ce10, however I'm having trouble understanding exactly how this is achieved in practice. Ive read the io features book here https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-51006.pdf where on page 7 I think it says that the 3.0-V LVTTL should have a 50 or 25 ohm impedance with or without calibration setting.

Ive also read through the section on io banks in the cylone iv e handbook here https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyclone4-handbook.pdf, but not found any more information on how to actually set the 50 ohm output.

Is it just a case of in the pin planner in quartus prime, setting IO standard to 3.0-V LVTTL and thats it, as shown in my attached image? If so how can i be sure it is 50 and not 25?

Any other suggestions would be welcome if im missing the plot completely.

[rstofer]

If you actually had a driving impedance of 50 Ohms, adding a 50 Ohm load should drop the open circuit voltage in half.
Now, can the pin actually drive a total of 100 Ohms (50 internal and 50 external)?  Beats me.

You have to look at the maximum output current and calculate the minimum allowable load.

Somehow, Ohm's Law is going to play into this calculation...

[Daixiwen]

By default the output will not have any series termination. You need to enable it.
For that, in the pin planner, go to the lower part with the table, right click on the free area after the column titles, and click on "customize columns"


It will open a window where you can choose what columns to show for each pin. Find the "Output Termination" entry in the available columns and transfer it to the "show these columns" list with the little arrow button.


Then in the table you'll have a new column where you can choose what kind of termination you want.


You will see by default all the possible values, even those that aren't compatible with your I/O standard or your pin. So after you set this, run a I/O assignment analysis (processing menu in the pin planner) and see if it reports any error.

[AndyC_772]

If you actually had a driving impedance of 50 Ohms, adding a 50 Ohm load should drop the open circuit voltage in half.
Now, can the pin actually drive a total of 100 Ohms (50 internal and 50 external)?  Beats me.

A 50 ohm output on a device like an FPGA is normally used to drive a 50 ohm transmission line which terminates in a high impedance.

I talked in some depth about transmission lines with no termination, parallel termination and series termination here - it might be worth a read.

To the OP: go into the assignment editor and select:
"To" is the name of your output pin
"Assignment Name" is "Output Termination"
"Value" is "Series 50 Ohm"
"Enabled" = "Yes"

[TeddyPython]

Thank you for the very clear replies, much appreciated - my prototype is working almost as expected now! 

May I ask where you found this information? Is there a good guide on getting to grips with the software, or just a case of being familiar?

[Daixiwen]

No sorry I don't remember how I got this information. I've been using Quartus for too long
You just need to get familiar with it. The documentation is good but massive. You'll only end up using like 5% of the tool, but those 5% are different for everyone, depending on their application, so it's not easy to find a good tutorial or documentation tailored to your needs.

[AndyC_772]

Same here, I've been using Altera FPGAs since the days of MAXPLUS2, which was Quartus's predecessor.

[radiolistener]

You will see by default all the possible values, even those that aren't compatible with your I/O standard or your pin. So after you set this, run a I/O assignment analysis (processing menu in the pin planner) and see if it reports any error.

Does it actually affects synthesis result? Or it just will be used for post-synthesis timing analysis, just to check if timing constraints are meet?

[Daixiwen]

No it won't affect synthesis nor timing analysis.
If you make any changes to the pin assignments that could cause sensible differences in signal delay, you must make Quartus generate the IBIS models for you, then simulate your PCB with the correct IBIS model, get the signal delay from the simulation, incorporate it back in the timing constraints and then recompile your project. It should still not affect synthesis results but it will affect the fitter.
But unless it's a very tight timing signal or a very long propagation delay on the PCB it's usually not necessary to do all this.