Unspecified I/O standard in vivado when trying to set AXI gpio to 1 bit width

[Dmeads]

Hi all

trying to set my axi gpio blocks to 1 bit each but got this message when generating bitstream.

[DRC NSTD-1] Unspecified I/O Standard: 5 out of 135 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: io5_tri_o[0], LED4_tri_o[0], LED1_tri_o[0], switch_tri_i[0], and BTN1_tri_i[0].

I don't even have these ports in my axi gpio when I click on it.

here is my block diagram and constraints file:

Code: [Select]

##switch
set_property -dict { PACKAGE_PIN M20  IOSTANDARD LVCMOS33 } [get_ports { switch }];

##led4
set_property -dict { PACKAGE_PIN L15    IOSTANDARD LVCMOS33 } [get_ports { LED4 }];

##led1
set_property -dict { PACKAGE_PIN P14    IOSTANDARD LVCMOS33 } [get_ports { LED1 }];

##BTN1
set_property -dict { PACKAGE_PIN D20    IOSTANDARD LVCMOS33 } [get_ports { BTN1 }];

##io5
set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { io5  }];

[asmi]

That's because these ports are always arrays (even if they contain only single wire - [0:0]), so your constraints need to be something like this:
set_property -dict { PACKAGE_PIN M20  IOSTANDARD LVCMOS33 } [get_ports { switch[0] }];
Moreover, you didn't specify port directions in your GPIO IPs, hence all ports are exported as tristate (this is where suffix _tri comes from in the port name). Small hint - if you open the wrapper file, you will see actual port names as they need to appear in constraints file.
Fix these things, and it should be good to go.