Verilog generate and buses

[EugenioN]

Hi all!
I found myself stuck into a simple problem I cannot describe in verilog!
I have 12 buses, each 16 bit wide, and I should 'or' them to create a single, 16 bit wide bus:

Code: [Select]

wire [15:0] this_sixteen_bits_data[11:0];
wire [15:0] output_data;

this_sixteen_bits_data[0]=some_logic_instance_0;
this_sixteen_bits_data[1]=some_logic_instance_1;
...
this_sixteen_bits_data[11]=some_logic_instance_11;

assign output_data = this_sixteen_bits_data[0] | this_sixteen_bits_data[1] | ... | this_sixteen_bits_data[11];

Trying not to go this verbose, a generate loop should be the way to go:

Code: [Select]

wire [15:0] this_sixteen_bits_data[11:0];
wire  [15:0] output_data;

genvar i;
generate
for (i=0; i<12; i=i+1) begin : wide_or_genvar
this_sixteen_bits_data[i]=some_logic[i];
output_data = ??? this_sixteen_bits_data[i];
end
endgenerate

How can you describe this parallel wide-or inside a generate loop?

[asmi]

Not sure what you need generate for in this case, or anything else. Just use a simple bitwise OR (|):

Code: [Select]

result = bus[0] | bus[1] | ... | bus[11];
Please do not confuse logical OR (||) with bitwise OR(|). There is also an unary version of OR (|some_var), which is also called "folding" or "reduction" operator, since it "folds" the multibit argument into a single bit. Some more reading here: https://verilogcodes.blogspot.com/2015/10/unary-or-reduction-operators-in-verilog.html

[ejeffrey]

In addition to what asmi explained, even if you want to do this with a loop you don't need a generate block.  A regular for loop inside a combinatoric process is enough.

Generate for is mostly only needed when you need to create multiple copies of a submodule instance or a top level process. 

[EugenioN]

Not sure what you need generate for in this case, or anything else. Just use a simple bitwise OR (|):

Code: [Select]

result = bus[0] | bus[1] | ... | bus[11];


Yeah, this is my actual implementation.
I don't like the cut&paste/verbose approach. I was wandering if there is a more concise way to describe it.

[EugenioN]

In addition to what asmi explained, even if you want to do this with a loop you don't need a generate block.  A regular for loop inside a combinatoric process is enough.

Generate for is mostly only needed when you need to create multiple copies of a submodule instance or a top level process.

I'm actually creating multiple copies of module instances, each generating a 16bit wide result.
At the end, I need to (bitwise) 'or' those results in a single 16bit bus, so the generate loop is a 'free' resource I though I could take advantage of.

Anyhow, never tried the for loop for actual sintesizable logic (testbench only). How can i write down this with for loop?

Code: [Select]

wire [15:0] this_sixteen_bits_data[11:0];
wire [15:0] output_data;

assign output_data = this_sixteen_bits_data[0] | this_sixteen_bits_data[1] | ... | this_sixteen_bits_data[11];

[Someone]

wor

or a variable in the loop

[langwadt]

In addition to what asmi explained, even if you want to do this with a loop you don't need a generate block.  A regular for loop inside a combinatoric process is enough.

Generate for is mostly only needed when you need to create multiple copies of a submodule instance or a top level process.

I'm actually creating multiple copies of module instances, each generating a 16bit wide result.
At the end, I need to (bitwise) 'or' those results in a single 16bit bus, so the generate loop is a 'free' resource I though I could take advantage of.

Anyhow, never tried the for loop for actual sintesizable logic (testbench only). How can i write down this with for loop?

Code: [Select]

wire [15:0] this_sixteen_bits_data[11:0];
wire [15:0] output_data;

assign output_data = this_sixteen_bits_data[0] | this_sixteen_bits_data[1] | ... | this_sixteen_bits_data[11];

something along the the line of this:

Code: [Select]

reg [15:0] output_data;
integer i;
always@(*)
begin
  output_data = 16'h0;
  for(i = 0; i < 16; i=i+1)
    output_data = output_data | this_sixteen_bits_data[i];
end



[EugenioN]

something along the the line of this:

Code: [Select]

reg [15:0] output_data;
integer i;
always@(*)
begin
  output_data = 16'h0;
  for(i = 0; i < 12; i=i+1)
    output_data = output_data | this_sixteen_bits_data[i];
end



Worked great, thank you!