Wrong voltage DDR3 chip on Arty A7 board?

[vstrakh]

Hi all.

Going through Digilent templates for memory interface generator in Vivado, it selects the MT41K128M16-15 part running at 1.35v, yet on the board I see the Micron part with FBGA code D9PSL, which matches the different chip - 1.5v MT41J128M16-125.
Schematic lists 1.35v part, there is a resistors load table with options for DDR3 VCC, and on the board I see the PMIC is configured for 1.35v.
The template puts the chip at 333MHz (666MT/s), way below its rated speed of 800MHz (1600MT/s), and the MIG won't even let you select anything higher than 400MHz.

So, am I in any kind of trouble? The chip is massively underclocked, but the VCC is also below specs. Should it work without problems?

[asmi]

Hi all.

Going through Digilent templates for memory interface generator in Vivado, it selects the MT41K128M16-15 part running at 1.35v, yet on the board I see the Micron part with FBGA code D9PSL, which matches the different chip - 1.5v MT41J128M16-125.
Schematic lists 1.35v part, there is a resistors load table with options for DDR3 VCC, and on the board I see the PMIC is configured for 1.35v.

That is not going to work. DDR3L (1.35V) devices are backwards compatible with DDR3 (1.5V), but not the other way around. Check with Digilent.

The template puts the chip at 333MHz (666MT/s), way below its rated speed of 800MHz (1600MT/s), and the MIG won't even let you select anything higher than 400MHz.

So, am I in any kind of trouble? The chip is massively underclocked, but the VCC is also below specs. Should it work without problems?

That is normal, Artix can only drive DDR3L up to 400 MHz.

[vstrakh]

Well, it appears the DDR3 is working.

I had no experience with Vivado block designs before, it took a bit of time to push through few obscure critical warnings (clocks redefined /not matching inside the MIG-generated IP), but in the end the Microblaze is running, and the Xil_TestMem32() reports successful memory test on the whole 256MB range on many iterations.

I do totally agree that you do not design stuff around DDR3L and then drop in random DDR3 chip. It's violation of all the rules there are, and just playing a roulette.
But looking at the unjustified "DDR3 undervolting" experiments some people are doing with their PCs I was hoping the same effects can generally apply here too.

I've no idea about the resulting stability margins, but at least it appears to be working for now...

[asmi]

I do totally agree that you do not design stuff around DDR3L and then drop in random DDR3 chip. It's violation of all the rules there are, and just playing a roulette.
But looking at the unjustified "DDR3 undervolting" experiments some people are doing with their PCs I was hoping the same effects can generally apply here too.

That's super weird, I would highly recommend contacting Digilent for the explanation, unless you got it second-hand, in which case the memory module was likely replaced. In the latter case I would buy a correct part and replace it myself.

I've no idea about the resulting stability margins, but at least it appears to be working for now...

DDR3L has even lower margins than DDR3, so I would be seriously concerned with stability. FPGA designs sometimes are super-hard to debug even without additional complications of HW issues.

[vstrakh]

unless you got it second-hand, in which case the memory module was likely replaced. In the latter case I would buy a correct part and replace it myself.

Yeah, it's second-hand one, that's why I can't just request explanations from Digilent.
It looks super clean though, the white solder mask has no discoloration or burns, no smd parts dislocated (tens of tiny resistors/caps underneath the DDR3 chip), no pin headers melting or deformations, and the tin surface looks uniform and identical all across the board.

Soldering BGA's is beyond my current capabilities.

[asmi]

Yeah, it's second-hand one, that's why I can't just request explanations from Digilent.
It looks super clean though, the white solder mask has no discoloration or burns, no smd parts dislocated (tens of tiny resistors/caps underneath the DDR3 chip), no pin headers melting or deformations, and the tin surface looks uniform and identical all across the board.

If the job was done by an experience technician, you won't notice any difference.
Can you please post a high-resolution photo of your board? I'm curious now

Soldering BGA's is beyond my current capabilities.

You can buy a replacement chip and take it to the closest electronics repair shop - it should only take a few minutes for a qualified person.

[vstrakh]

Not the best lighting, packages and connectors cast shadows, but here it is.

The FPGA surface had traces of thermal paste, this may or may not indicate previous user had stability issues, maybe previous owner was doing some heavy processing and wanted it cooler. Running DDR3 test I see XADC reports FPGA temperature as 56-58 deg (at 28 deg ambient temperature).

Unfortunately with the ongoing russian aggression replacing DDR3 is not a viable option. Even in better times buying $5 part on Mouser would add $40 for delivery and customs, and this would be almost a half of what I paid for this board. Currently it's disrupted at many levels.

If/When I will see the issues with stability, my other option would be to relocate the resistor from R266 to R261 (on the photo right above the switches SW3 and SW2, at the bottom of the top view pic). According to schematics this should reconfigure PMIC for 1.5v DDR VCC.

[asmi]

Not the best lighting, packages and connectors cast shadows, but here it is.

Bizzare According to official pictures the correct part is supposed to have marking D9PSK, so just one letter difference from yours. But this board has been in production for many years, and I have a version which was called simply "Arty" - because at the time there were no other boards in that family, and so over time it went through many changes - for example, my board uses ADP5052 as a main PMIC instead of Renesas one which it currently uses.

The FPGA surface had traces of thermal paste, this may or may not indicate previous user had stability issues, maybe previous owner was doing some heavy processing and wanted it cooler. Running DDR3 test I see XADC reports FPGA temperature as 56-58 deg (at 28 deg ambient temperature).

I highly recommend you to install a heatsink on your chip. From my experience, even 50T device can seriously heat up if you load it up, and unlike modern CPUs, these FPGA do NOT have builtin thermal protection and will happily go into a thermal runaway and fry themselves. I've seen a 50 device go beyond 70°C in a matter of a couple of minutes - before I noticed it and shut it down, 100T device that is going to be even worse. Whenever I design a board with A100T device nowadays, I always add a provision for a fan as a number of my boards were/are used in thermally-challenged conditions of limited airflow and so just a heatsink was not enough in some cases.

If/When I will see the issues with stability, my other option would be to relocate the resistor from R266 to R261 (on the photo right above the switches SW3 and SW2, at the bottom of the top view pic). According to schematics this should reconfigure PMIC for 1.5v DDR VCC.

Actually I would recommend you to do it because this way you can run your memory at 400 MHz, and not at 333 MHz which is the case for DDR3L.

[langwadt]

I highly recommend you to install a heatsink on your chip. From my experience, even 50T device can seriously heat up if you load it up, and unlike modern CPUs, these FPGA do NOT have builtin thermal protection and will happily go into a thermal runaway and fry themselves. I've seen a 50 device go beyond 70°C in a matter of a couple of minutes - before I noticed it and shut it down, 100T device that is going to be even worse. Whenever I design a board with A100T device nowadays, I always add a provision for a fan as a number of my boards were/are used in thermally-challenged conditions of limited airflow and so just a heatsink was not enough in some cases.

afair you can turn on overtemperature powerdown with a bit stream option

[asmi]

afair you can turn on overtemperature powerdown with a bit stream option

You learn something new every day! Thanks for the info! From UG480:

By default, the automatic shutdown feature is disabled for designs that do not use XADC. If XADC is instantiated, the automatic shutdown feature can be disabled either by setting the OT signal within Config Reg 1 (41h) High, or by adding the following constraint to the project XDC file:
set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN DISABLE [current_design]

I never actually used ADC (except indirectly as part of DDR3 memory controller, or over JTAG to monitor temperature), so no wonder I didn't know about that. Still, default overtemp is set to 125°C, which is way too high for commercial grade devices.

[vstrakh]

Just for the lulz reconfigured the controller for 400MHz.
Selected 1.5v option in MIG to allow 2500ps clock period, changed the standards from SSTL135 to SSTL15 to force the MIG through pinout validation, ignoring the fact the FPGA bank and DDR is powered with 1.35v.
The tests are still passing...

[colorado.rob]

Just for the lulz reconfigured the controller for 400MHz.
Selected 1.5v option in MIG to allow 2500ps clock period, changed the standards from SSTL135 to SSTL15 to force the MIG through pinout validation, ignoring the fact the FPGA bank and DDR is powered with 1.35v.
The tests are still passing...

It may work fine at room temperature, but may not pass across the full specified temperature range.

[asmi]

It may work fine at room temperature, but may not pass across the full specified temperature range.

It may still just work though. Xilinx characterization is VERY conservative, that is meant to ensure it works in all cases (imagine the bad PR which would ensue if their FPGA will suddenly stop working on a NASA space probe en route to some far away destination!). Infact it's so conservative that you can "pretend" a speed grade 1 device to be a speed grade 2 device and program it as such, and it will still very likely work just fine, perhaps just heating a bit more than usual. Of course this is not something I'd recommend to use for commercial applications, but for hobbyists and R&D projects I see no problems. For example, I have a personal experience of overclocking Z015-1 part to speed grade 2, and it worked just fine, even GTPs worked at 5 Gbps in PCIE 2.0 x2 mode (that's how the board was wired, so couldn't check x4) with no problems whatsoever (and I confirmed that it was infact operating at PCIE 2.0 speeds).

[langwadt]

Just for the lulz reconfigured the controller for 400MHz.
Selected 1.5v option in MIG to allow 2500ps clock period, changed the standards from SSTL135 to SSTL15 to force the MIG through pinout validation, ignoring the fact the FPGA bank and DDR is powered with 1.35v.
The tests are still passing...

the titan sub also went to the titanic a few times

[vstrakh]

the titan sub also went to the titanic a few times

Of course it's not for production or anything important at all
I was curious about how fragile the whole situation is, and it seems for some lab works and occasional ideas checks it will be just fine, as if I didn't notice the DDR3 chip is different.