FPGA VGA Controller for 8-bit computer

[asmi]

Oh. My. Gawd. 

Xilinx isn't selling itself to me at the moment.  I've just spent the last hour trying to get the damn ISE software to install and load so that I might have a play with my Spartan-6 over the weekend.  I'll be damned if I'm uninstalling my Oracle VM software just so that the ISE can run its own (older version) VM environment.  WTH is that for, anyway?  Upshot is that I'm currently downloading an older version of the ISE in the hope it's the non-VM version.  Then I've got to apply a hack to get it to work in Windows 10.

Be as critical as you want about Antel, but Quartus just works.

ISE was last updated like 10 years ago, and currently it's on a life support. So avoid it unless you have to support your old products using these things.

I was talking about 7 series devices (Spartan-7/Artix-7) - they are supported by modern Vivado (or Vitis as the combined HW-SW package is called now). Which not only "just works", but also offers a ton of additional stuff for free.

[nockieboy]

Oh. My. Gawd. 

Xilinx isn't selling itself to me at the moment.  I've just spent the last hour trying to get the damn ISE software to install and load so that I might have a play with my Spartan-6 over the weekend.  I'll be damned if I'm uninstalling my Oracle VM software just so that the ISE can run its own (older version) VM environment.  WTH is that for, anyway?  Upshot is that I'm currently downloading an older version of the ISE in the hope it's the non-VM version.  Then I've got to apply a hack to get it to work in Windows 10.

Be as critical as you want about Antel, but Quartus just works.

ISE was last updated like 10 years ago, and currently it's on a life support. So avoid it unless you have to support your old products using these things.

I was talking about 7 series devices (Spartan-7/Artix-7) - they are supported by modern Vivado (or Vitis as the combined HW-SW package is called now). Which not only "just works", but also offers a ton of additional stuff for free.

Yeah I know, I was just trying to get ISE set up so I could try out the Spartan-6 board I have.  It's a shame they aren't using the same software for both the 6- and 7-series - I'll get so far using the ISE for the Spartan-6 before I'd likely have to change up to Vivado for a Spartan-7.

It's just not a great marketing decision when you close off older products like the 6-series, which just happen to be cheap as chips for beginners to learn on, behind software that is difficult to install and run, and I was venting a little.  Don't get me wrong, they've done exactly the same thing with Quartus and the Cyclone series (amongst others), but the old software (and the new) just installs and works, simple as that, which reduces the hoops a beginner has to jump through.

[BrianHG]

@Nockieboy, you will need this IC for your HDMI port's ESD protection and 5v <> 3.3v conversion for the DDC I2C lines.
https://www.ti.com/product/TPD12S520
Thanks for Asmi, I had the wrong one... Here is Asmi's correction:
https://www.ti.com/product/TPD12S521

For the FPGA driving this chip, you will need a group of 8 series resistors.  You can use this resistor pack:
https://www.digikey.com/en/products/detail/yageo/YC248-JR-0733RL/1005206
Or, 8 individual 0402 33ohm resistors.

@83 cents, getting rid of the TFP410, VGA dac & sync driver 74HC245 will cut costs on your PCB getting rid of a lot of junk and save PCB space and a routing nightmare.
Also, you will now have room for a full DDR2/3 ram chip.

The IO bank needs to be a normal 3.3v and have 8x ####DQ## pins for the video signal + 4 more cheap regular IOs for the DDC I2C, HPD sense & CEC.  (Go figure, 12 IOs total...)

[asmi]

Yeah I know, I was just trying to get ISE set up so I could try out the Spartan-6 board I have.  It's a shame they aren't using the same software for both the 6- and 7-series - I'll get so far using the ISE for the Spartan-6 before I'd likely have to change up to Vivado for a Spartan-7.

It's just not a great marketing decision when you close off older products like the 6-series, which just happen to be cheap as chips for beginners to learn on, behind software that is difficult to install and run, and I was venting a little.  Don't get me wrong, they've done exactly the same thing with Quartus and the Cyclone series (amongst others), but the old software (and the new) just installs and works, simple as that, which reduces the hoops a beginner has to jump through.

Yea, I get the inconvenience, but the thing is 7 series is better in every way - it's much faster than S6, it's cheaper if you compare the same densities (at least in "official" channels like Digikey or Mouser), and Vivado is much more functional. Supporting legacy is always pain in the butt (and as a software developer I know this from my own experience), so they had to draw a line somewhere. Since first devices of a 7 series rolled out, they released two newer generations of FPGA (Ultrascale and Ultrascale+), but these are high-end parts which go from "simply expensive" to "insane" at over 100K$ per device!! There are few outliers like smallest Zynq Ultrascale+ SoCs (2/4 ARM64 cores + FPGA fabric in a single chip) which can be had for few hundred bucks, but in general they are priced at least in 4 figures. Don't get me wrong - these are great devices (high performance, insane amount of resources, some really cool HW features), they are just waaaay out of my price range.

[asmi]

@Nockieboy, you will need this IC for your HDMI port's ESD protection and 5v <> 3.3v conversion for the DDC I2C lines.
https://www.ti.com/product/TPD12S520

No, this chip is for the receiver port. For transmitter port use this one: https://www.ti.com/product/TPD12S521 Few pages back I've posted connection schematic, but I took it straight from the datasheet.

For the FPGA driving this chip, you will need a group of 8 series resistors.  You can use this resistor pack:
https://www.digikey.com/en/products/detail/yageo/YC248-JR-0733RL/1005206
Or, 8 individual 0402 33ohm resistors.

Were you able to find a connection schematic for CV driving HDMI directly? All that I could find was either using transceivers + retimer, or interface chip a-la TFP410.

[BrianHG]

The Cyclone IV can't handle 135MHz without some (serious, I'm guessing) work on the HDL.  I wonder if the Cyclone V will be any better?

The problem actually isn't with the 135MHz, when addressing that core ram it will be retaining the 270MHz let alone 250MHz.  The massive free gates on the CycloneV will give the compiler space to generate a 135MHz core easily.  To Achieve the 250/270MHz core dualport ram the entire size of the chip, we will probably need to add 1 additional clock cycle on the write data port, or read data port.  At absolute worst, on both sides.  This wont effect functionality as the core was already written to handle a 'PIPLINE' parameter which we have located in all the right places for easy accommodation.

The second choice is to switch from maximum 15 layers to maximum 12 layers where the core will now be 200/216MHz as I described a few posts back.  (IE 100/108MHz for the geometry engine)

Since with the DDR2/3 ram, you will get another 2 layers, you would be going from 17 layers to 14 layers.

Note that my old CycloneIII video scaler image processor had a 216MHz core, though, it processed 6 1080p video images, 3 in 2 out in parallel.  It also had 4GB or 128bit DDR2 ram on SODIMM modules.

[BrianHG]

For the FPGA driving this chip, you will need a group of 8 series resistors.  You can use this resistor pack:
https://www.digikey.com/en/products/detail/yageo/YC248-JR-0733RL/1005206
Or, 8 individual 0402 33ohm resistors.

Were you able to find a connection schematic for CV driving HDMI directly? All that I could find was either using transceivers + retimer, or interface chip a-la TFP410.

Altera's LVDS signal levels and strengths can be configured to match an Artix6 LVDS IO port where I found an example HDMI direct transmitter which uses 33 ohm series resistors and the circuit expects the receiving display to have a 50ohm termination.

Though Intel does support HDMI/DP direct on the Cyclone 10 with a free HDMI transmitter megafunction, it pains me that they don't have any schematics laying around, yet, they do have scope shots and timing eye diagrams of the FPGA plugged into an analyzer.

By all counts, in theory, Nockieboy just needs to configure Intel's HDMI transmitter generator megafunction to the right IOs and PLL and it should make him an HDMI video signal from the GPU's parallel 24bit video data + syncs output port.  I did not read enough to see if it supported embedded audio.  If not, Nockieboy will need to code his own.  At least the standard 48KHz audio format will be compatible with the DAC he will be using when using 480p or 720p.

[asmi]

Though Intel does support HDMI/DP direct on the Cyclone 10 with a free HDMI transmitter megafunction, it pains me that they don't have any schematics laying around, yet, they do have scope shots and timing eye diagrams of the FPGA plugged into an analyzer.

DisplayPort is different because it uses "normal" ac-coupled differential lines without any DC offset (like pretty much all other high-speed serial standards do - SATA, PCIE, USB 3.x and many others), and with 100 Ohm differential termination at the receiver side, while HDMI uses single-ended 50 Ohm termination to 3.3 V for both sides of a diff pair independently.
 
In Xilinx world TMDS is actually often used as a poor man's LVDS when you have no control over Vccio (say you have a devboard and can't change it), as "normal" LVDS requires 2.5 V Vccio, while TMDS is the only differential IO standard that works at 3.3 V Vccio - and vast majority of affordable devboards out there power Vccio with that voltage.

Xilinx has "UG471 - 7 Series FPGAs SelectIO Resources User Guide" which covers all supported IO standards, including available (or required as the case may be) termination schemes, additional parameters and stuff like that - basically it contains everything you will ever need to know about using IO cells and all modules that are contained into them (like SERDES, DDR cells or delay blocks). Does similar user guide exist for CV devices? If it does, that's where I'd go for details about TMDS implementation.

By all counts, in theory, Nockieboy just needs to configure Intel's HDMI transmitter generator megafunction to the right IOs and PLL and it should make him an HDMI video signal from the GPU's parallel 24bit video data + syncs output port.  I did not read enough to see if it supported embedded audio.  If not, Nockieboy will need to code his own.  At least the standard 48KHz audio format will be compatible with the DAC he will be using when using 480p or 720p.

Is this megafunction available for free, or you have to pay for it?

[BrianHG]

Yes, we will be using the cheap 3.3v powered IO bank trick for HDMI, though I bet 2.5v would also work since in the displays, there are adaptive cable length equalizers.

Section 5 here has the long version of the programmable IO specs:
https://www.intel.com/content/www/us/en/programmable/documentation/sam1403481100977.html#sam1403477508169

If we wanted DP's AC coupling we might need to use onboard terminators.

Specific IO drive capabilities here:
https://www.intel.com/content/www/us/en/programmable/documentation/mcn1422497163812.html#mcn1419933398989

After checking the above (Periphery Performance), I was wrong, the CV-7 is specified to clock out 740mbps on any true differential IO pair.  That's only a puny 2.5Mhz slower than 720p's 742.5mbps.  CV-6 can go up to  840mbps.  I believe 720p will work without issue.

[asmi]

Section 5 here has the long version of the programmable IO specs:
https://www.intel.com/content/www/us/en/programmable/documentation/sam1403481100977.html#sam1403477508169

Thanks for the link - this is what I was looking for! Why it's so hard to find via google? Xilinx user guides almost always pop up on the first page of google results...

Yes, we will be using the cheap 3.3v powered IO bank trick for HDMI, though I bet 2.5v would also work since in the displays, there are adaptive cable length equalizers.

That's not gonna work - according to your link, all differential output drivers require Vccio of 2.5 V or lower, and I finally got my answer that TMDS indeed is not supported directly. That explains my lack of success in trying to find a schematic for direct connection... This sucks all around At this point I personally wouldn't risk spinning a board with "invented by me" solution until I built some kind of prototype using any existing devboard and seen it actually working and connected display actually showing something.
One more reason to jump the ship

[BrianHG]

By all counts, in theory, Nockieboy just needs to configure Intel's HDMI transmitter generator megafunction to the right IOs and PLL and it should make him an HDMI video signal from the GPU's parallel 24bit video data + syncs output port.  I did not read enough to see if it supported embedded audio.  If not, Nockieboy will need to code his own.  At least the standard 48KHz audio format will be compatible with the DAC he will be using when using 480p or 720p.

Is this megafunction available for free, or you have to pay for it?

It's available and I can enter it into Nickieboy's GPU.  I need to wire it to IO pins and compile it to see, but his current 144pin IC doesn't have enough differential IOs free.

On Intel's site, it points to 'Premier' which means pay.

Below, I found a Displayport adapter IO board for the -GX versions of the FPGA.  The are using only the 2 series resistors, but probably the IOs are configured and powered at 2.5v.

[asmi]

It's available and I can enter it into Nickieboy's GPU.  I need to wire it to IO pins and compile it to see, but his current 144pin IC doesn't have enough differential IOs free.

You don't need to have an actual FPGA in hands to run P&R and see if it closes the timing. Just pick the device that it currently planned to be used on a new board, and see if you can fit everything and close timing.

Below, I found a Displayport adapter IO board for the -GX versions of the FPGA.  The are using only the 2 series resistors, but probably the IOs are configured and powered at 2.5v.

If my memory serves me DisplayPort specifies 1.62 Gbps per lane minimum bandwidth so that adapter has to use dedicated transceivers and not regular user IO pins, as none of the latter are fast enough.

[BrianHG]

If you want to re-buffer the LVDS from the CV, you can use this chip:
https://www.digikey.com/en/products/detail/texas-instruments/TDP158RSBR/7312817

It also has the level I2C shifter and seems to not require and ESD module.

Still cheaper than the TFP410, but no longer 83cents.

[BrianHG]

You don't need to have an actual FPGA in hands to run P&R and see if it closes the timing. Just pick the device that it currently planned to be used on a new board, and see if you can fit everything and close timing.

Below, I found a Displayport adapter IO board for the -GX versions of the FPGA.  The are using only the 2 series resistors, but probably the IOs are configured and powered at 2.5v.

If my memory serves me DisplayPort specifies 1.62 Gbps per lane minimum bandwidth so that adapter has to use dedicated transceivers and not regular user IO pins, as none of the latter are fast enough.

Yup, it's the drive capability and the CV though slower can create the same differential voltage and current on it's 740mhz differential outputs.  Just not the same speed or rise and fall characteristics.

The above buffer chip will guarantee an HDMI compliant cable drive levels and the CV's differential output is fast and clean enough for 480p & 2.5mhz shy of 720p unless we use a CV-6 speed grade.

(*** But, it needs some I2C settings...)

There are probably cheaper HDMI buffer/translators since we only need regular 1080p performance.

[BrianHG]

Found one, dirt cheap, under 1$:
https://www.digikey.com/en/products/detail/nxp-usa-inc/PTN3366BSMP/5981060?s=N4IgTCBcDaIAoBUByBmFA2dIC6BfIA

We are now on-par with the 83cent ESD IC, except this NXP has an adaptive amp which only needs a 700mv swing from the source, AC coupled meaning it don't care about DC offset.  Well within CV's differential LVDS output drive capabilities.

Level shifter for DDC and HPD.

No controls other than a 2 bit fixed pre-emphasis gain control.
Straight traces to boot!

Actually now, VLF DC signals are bothering me...
Maybe the series DC filter caps may be omitted, or at least replaced with series resistors depending on the amp's internal 'input bias' voltage on it's internal termination resistors.

[nockieboy]

Found one, dirt cheap, under 1$:
https://www.digikey.com/en/products/detail/nxp-usa-inc/PTN3366BSMP/5981060?s=N4IgTCBcDaIAoBUByBmFA2dIC6BfIA

We are now on-par with the 83cent ESD IC, except this NXP has an adaptive amp which only needs a 700mv swing from the source, AC coupled meaning it don't care about DC offset.  Well within CV's differential LVDS output drive capabilities.

Level shifter for DDC and HPD.

No controls other than a 2 bit fixed pre-emphasis gain control.
Straight traces to boot!

Trying to catch up with the conversation, I'm like

So this won't need the terminating resistors, or the ESD protection?  Looks like another darn QFN to me, though.   I think I'm more concerned about soldering those than the BGAs! 

[BrianHG]

Found one, dirt cheap, under 1$:
https://www.digikey.com/en/products/detail/nxp-usa-inc/PTN3366BSMP/5981060?s=N4IgTCBcDaIAoBUByBmFA2dIC6BfIA

We are now on-par with the 83cent ESD IC, except this NXP has an adaptive amp which only needs a 700mv swing from the source, AC coupled meaning it don't care about DC offset.  Well within CV's differential LVDS output drive capabilities.

Level shifter for DDC and HPD.

No controls other than a 2 bit fixed pre-emphasis gain control.
Straight traces to boot!

Trying to catch up with the conversation, I'm like

So this won't need the terminating resistors, or the ESD protection?  Looks like another darn QFN to me, though.   I think I'm more concerned about soldering those than the BGAs! 

No term resistors.  See the data sheet, though, you will need 8 series 0402 caps.  Not a nightmare...

Same hot air + you can use a normal soldering irons to fix bad connecting pins.  It's actually easier than your current 144pin TQFP since you cannot damage any pins.  See here: https://youtu.be/BvhE16vBfX4

Just make sure the PCB footprint you use has long pins like in the video.  Though, they do not need to be that long.

Even  Farnell element14 has the PTN3366BSMP dirt cheap.
And you know that amp IC will drive an HDMI cable at full length.
And with this setup, you should be able to drive a 720p signal through the cable if you like.

[asmi]

That solution still kind of smells to me because of too many unknowns for my taste. If I would be doing it, I would build a quick prototype first with just that HDMI out circuit and connect it to one of my devboards to check that it will actually work, before committing to a full board. So I think you should consider laying out a quick prototype and check it up.

[BrianHG]

That solution still kind of smells to me because of too many unknowns for my taste. If I would be doing it, I would build a quick prototype first with just that HDMI out circuit and connect it to one of my devboards to check that it will actually work, before committing to a full board. So I think you should consider laying out a quick prototype and check it up.

Not a bad idea.  Nockieboy does have a C-IV dev board (though traces aren't matched length to IO expander connectors) and a cheap 5$ 2 layer PCB with this, IC and HDMI connector & a few SMD caps would cost under 15$ total.
He just needs to generate simple color bars and sound, IE using his existing sync gen with hard-generated test pattern -> home coded HDMI encoder -> 10:1 serializer.
I know you shouldn't expect anything other than 480p to work under these un-matched trace length feeding the amp circumstances, but maybe even 720p might make it through with this buffer amp which will generate a balanced output.

[nockieboy]

Yes I'd been thinking about putting a test PCB together to confirm that the solution works, I just didn't know if the unmatched, non-paired traces going through header pins on the dev board to a second PCB would create more problems.  If I can get 480p out of the dev board, then I'd be totally happy getting rid of the VGA output on the new GPU card.

It'll delay the actual GPU card production by a few weeks/month, but I think it's worth it for my peace of mind and will give me some time to focus back on finishing the ellipse drawing function.

Just need to confirm that the dev board has the right IOs available for the job, though.  Have attached the schematics for the dev board I'm using.

[BrianHG]

Yes I'd been thinking about putting a test PCB together to confirm that the solution works, I just didn't know if the unmatched, non-paired traces going through header pins on the dev board to a second PCB would create more problems.  If I can get 480p out of the dev board, then I'd be totally happy getting rid of the VGA output on the new GPU card.

It'll delay the actual GPU card production by a few weeks/month, but I think it's worth it for my peace of mind and will give me some time to focus back on finishing the ellipse drawing function.

Just need to confirm that the dev board has the right IOs available for the job, though.  Have attached the schematics for the dev board I'm using.

Look at FPGA pins -> Header P2 pins: (use 4 adjacent pairs for the HDMI digital data)
38p/39n -> 38/37
49p/50n -> 32/31
52p/53n -> 29/28
54p/55n -> 27/26
59p/60n -> 24/23
ARRRRGGGG, these IO also go to a SDRAM chip according to the schematic...  Maybe cut the traces or remove the ram chip...

You only need 4 of these pairs.  They are all located on header 'P2'.
The other signals, I2C & HPD and output enable control & gain signals may be wired to any other IOs.

I would make a narrow PCB which sits on the P2 Header itself.  Make sure you can make JLPCB's cheap 5$ for 5PCBs fit on that connector.  It may need to be a bit narrower which is why I listed all the possible matched N/P pairs.

Also, make sure you have the ability to change the dev-board's 3.3v regulator for a 2.5v since we will use want to use that IO voltage on the Cyclone V.  NXP's amplifier chip only requires a differential 300mv signal coming in to drive the full TMDS output.  It has auto level, auto gain and a 4 level set-able high frequency/edge enhancement boost capability set by 2 input pins.

Your test PCB should have the 8 series caps like in the schematic, but, it should also have 4 parallel load resistors just before the caps as an extra termination option.  Also, the HDMI TMDS outputs should have test points, even though garbled, at least your 25MHz scope should be able to see the TMDS pixel clock line which is also 25MHz.

All other IOs should be wired as shown in the NXP datasheet.

Note that CycloneV no longer has the lower/higher FMAX speed restrictions of some IO banks compared the CycloneIV, so, some of the n/p pairs we have chosen have a 500MHz limit unlike the higher 740MHz LVDS limit of every differential pair on the CycloneV, so our goal here is 250MHz 480p and audio.  720p is not expected to work here.

Check the actual layout of your dev board so you may choose the straightest traces.  You may also swap the n&p as in the FPGA, the buffer would be driven with negative logic.  The important thing here is that you are using the pairs.


Again, check JLPCB's maximum dimensions for that 5$ for 5pcb deal and check if you can make a PCB which will at least to pin 32 of header P2.  Any extra space should just have a header going off the edge of the PCB and you should get a female dual inline header with gold plated pins to plug your test PCB onto the dev board.


Prep this PCB quick, then we can get onto doing the HDMI encoder and you also have the filled ellipse to finish in the geo unit.

Once confirmed, you can then edit the new CV GPU to your liking.

[BrianHG]

Look at FPGA pins -> Header P2 pins: (use 4 adjacent pairs for the HDMI digital data)
38p/39n -> 38/37
49p/50n -> 32/31
52p/53n -> 29/28
54p/55n -> 27/26
59p/60n -> 24/23
ARRRRGGGG, these IO also go to a SDRAM chip according to the schematic...  Maybe cut the traces or remove the ram chip...

Do you have a good image of the dev board so I can see this layout.
You may get lucky and only have to razor cut 8 traces depending on layout.

[BrianHG]

As a reference, here are the electrical IO characteristics/voltages & thresholds for the CV:
CycloneV datasheet

The termination connections for the different LVDS modes is in the normal CV handbook 1.

[asmi]

OK guys, since you liked my previous one, I have another proposal Whenever I start working with new (for me) FPGA, I always design and build a simple breakout devboard with the bare minimum components to run the FPGA, and some memory (as you usually can't connect it via connectors) and just a couple of LEDs and buttons. Here is what one of those boards look like:


This devboard contains 256Mx16 (512 Mbytes total) DDR3L memory device and a single dual-color LED. It also contains HDMI out because I had some spare FPGA and didn't want to leave them unused. But the most important feature of this devboard are those two connectors on the bottom. These are high-speed connectors designed specifically for differential signals, each connector contains 20 differential pairs rated for 6 Gbps and beyond (depending on stackup height), I use one pair for power, so 38 user IO pins total, which I implemented as 19 differential pairs per connector, and all of the pairs going to the same connector are length-matched. As you can see, because of the way it's wired, one of connectors only supports 1.8 V logic levels, while another one is configurable - the board gives options of 1.8 and 3.3 V via zero ohm resistor placement, but it's possible to connect external DC-DC converter with any Vccio.

As you can see, this devboard is quite versatile for prototyping despite it being very simple. These Samtec connectors are quite expensive, but they send out free samples to anyone - I requested a 10 pairs of those connectors and they sent them to me for free the next day, and even paid for express postage via UPS.

My proposal is for you to design and build a similar devboard for your FPGA of choice. Place the memory device on a board, and connect the rest of IOs to connectrors like the one I use. If you length match all lines going into a single connector, you can then build whatever addon boards with prototype circuits you need as this gives a lot of freedom. Also ensure at least one of those high-speed connectors has configurable Vccio voltage - again to add more versatility to the board. Since that devboard is going to contain the very minimal set of components, it shouldn't be very expensive to make, but I think it will prove itself useful many times over in the future - like did the devboard pictured in the beginning of this post. I understand that it's going to sidetrack this project even more, but again, I think it will be worth it at the end of the day.

[nockieboy]

Here's attempt No.1 for the DVI output card.  Have done what I can with it, but there's probably loads of things wrong with the power layout.  The entire bottom layer will be ground plane, aside from a few power traces to connect nets.  All signals on the top layer.  I probably need to add more decoupling caps to the top and spread out some power planes on the top layer?

PCB layout also included, very rough draft and I know I can make it smaller.  Not overly concerned about keeping it under the $5 mark, to be honest.  I'll be paying more for postage than I will for the PCBs, no matter what.  Might add a few LEDs and a PCM5101 to make it even more useful.