Then, get it simulating on Lattice Diamond.
Diamond now ships with Modelsim so that shouldn' t be a problem.
If you ever want to synthesize it with Diamond though, just a quick tip: as far as I saw, you're using SystemVerilog? Lattice LSE (Lattice own synthesis engine) doesn't support SystemVerilog AFAIK, so you'll need to use Synplify Pro instead. Diamond comes with both, so it's just a matter of selecting Synplify as the synthesis tool. Just so you don't waste time looking that up.
Yes it does, well it seemed to. I got my .SV ellipse generator & .BMP saver test bench working here working with ActiveHDL, so I know the 1 or 2 little changes needed:
https://www.eevblog.com/forum/fpga/systemverilog-example-testbench-which-saves-a-bmp-picture-and-executes-a-script/msg3465172/#msg3465172I also got my HDMI_PLL.SV going in Lattice's Synplify-Pro. It's their stupid arcane:
EHXPLLL HPLL0 (.CLKI(clk_in), .CLKFB(PLL0_clk_out[0]), // was an assigned wire (CLKOP_t)
.PHASESEL1(scuba_vlo0), .PHASESEL0(scuba_vlo0), .PHASEDIR(scuba_vlo0), .PHASESTEP(scuba_vlo0), .PHASELOADREG(scuba_vlo0),
.STDBY(scuba_vlo0), .PLLWAKESYNC(scuba_vlo0), .RST(scuba_vlo0),
.ENCLKOP(scuba_vlo0), .ENCLKOS(scuba_vlo0), .ENCLKOS2(scuba_vlo0), .ENCLKOS3(scuba_vlo0),
.CLKOP(PLL0_clk_out[0]), .CLKOS(), .CLKOS2(), .CLKOS3(),
.LOCK(LOCK0), .INTLOCK(), .REFCLK(REFCLK0), .CLKINTFB())
/* synthesis FREQUENCY_PIN_CLKOP = "WTF MUST THIS NUMBER HERE BE AN ASCII NUMBER IN QUOTES" */
/* synthesis FREQUENCY_PIN_CLKI = "WTF MUST THIS NUMBER HERE BE AN ASCII NUMBER IN QUOTES" */
/* synthesis ICP_CURRENT="6" */
/* synthesis LPF_RESISTOR="16" */;
defparam
HPLL0.CLKOS3_DIV = 1, HPLL0.CLKOS2_DIV = 1, HPLL0.CLKOS_DIV = 1,
HPLL0.CLKOP_DIV = PLL0_div, HPLL0.CLKFB_DIV = PLL0_mult, HPLL0.CLKI_DIV = 1,
HPLL0.CLKOS3_FPHASE = 0, HPLL0.CLKOS3_CPHASE = 0,
HPLL0.CLKOS2_FPHASE = 0, HPLL0.CLKOS2_CPHASE = 0,
HPLL0.CLKOS_FPHASE = 0, HPLL0.CLKOS_CPHASE = 0,
HPLL0.CLKOP_FPHASE = 0, HPLL0.CLKOP_CPHASE = (PLL0_div-1),
HPLL0.FEEDBK_PATH = "CLKOP", HPLL0.PLL_LOCK_MODE = 0,
HPLL0.OUTDIVIDER_MUXD = "DIVD", HPLL0.CLKOS3_ENABLE = "DISABLED",
HPLL0.OUTDIVIDER_MUXC = "DIVC", HPLL0.CLKOS2_ENABLE = "DISABLED",
HPLL0.OUTDIVIDER_MUXB = "DIVB", HPLL0.CLKOS_ENABLE = "DISABLED",
HPLL0.OUTDIVIDER_MUXA = "DIVA", HPLL0.CLKOP_ENABLE = "ENABLED",
HPLL0.PLLRST_ENA = "DISABLED", HPLL0.INTFB_WAKE = "DISABLED", HPLL0.STDBY_ENABLE = "DISABLED", HPLL0.DPHASE_SOURCE = "DISABLED",
HPLL0.CLKOS_TRIM_DELAY = 0, HPLL0.CLKOS_TRIM_POL = "FALLING", HPLL0.CLKOP_TRIM_DELAY = 0, HPLL0.CLKOP_TRIM_POL = "FALLING";
It's that stupid comment /* synthesis FREQUENCY_PIN_CLKOP/CLKI ="WTF MUST THIS NUMBER HERE BE AN ASCII NUMBER IN QUOTES" */ '
I cannot place a computed parameter there. Only a fixed ASCII number in quotes, otherwise Diamond says my PLL is illegal configured to 0MHz, and it stops there.
Lattice tole me just to use their Clarity Designer to make to PLL, but, I told them there were was a possibility of around 100 different PLL configurations and I would need Clarity to make ~100 .V files, and selectively include one instead of properly doing things a true software selection route.
Diamond may have been always automatically pushing my .SV code through SynplifyPro and it's just been accepting things so far. It would be kind of old and sad that Diamond cannot support at least an HDL language where I can use packed 2 dimensional registers.
Everything else I coded should be straight forward.
If a .V file would support a 2D array port, then my code is simple to change back to old fashioned Verilog.
EG:
reg [15:0] BANK_ROW_LOCATION [0:7] = '{0,0,0,0,0,0,0,0};
Instead of 'logic'
This is the only reason I have been using SystemVerilog. It's so I can have addressable regs like 8 x 16 bit bank_row_location s to scan in a simple for loop, or pass all 8 from 1 module to another.
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