FPGA VGA Controller for 8-bit computer

[nockieboy]

I looked at your schematic.
Are you sure you arent supposed to invert a signal?

I've just gone over it again and yes, it looks like the clock signal (INC) needs to be inverted. 

[nockieboy]

Also, make sure we didn't swap any of the +&- on the TMDS signals.  Any swapped signals need to be inverted in the Quartus Block Diagram Schematic since we cannot do so in the pin-planner.

Literally inverted? As in, insert an inverter between the 'top' module and the output pins for both _p and _n outputs on the clock signal pair?

[FenTiger]

Just swap the pins, i.e. connect tmds_clock_p to TMDS_CLK_n and vice versa.

[nockieboy]

Just swap the pins, i.e. connect tmds_clock_p to TMDS_CLK_n and vice versa.

Yeah, should have thought of that myself.  The _n pin wasn't explicitly defined in the schematic before, though - but now I've got it there, I can just swap the wires.

[BrianHG]

1 single inverter would have also worked...
How did the second pin appear?

[BrianHG]

Make sure on your scope that both the N&P output are oscillating with a 180degree phase difference.
You'll need 2 probes and need to turn on the horizontal time-base x10 magnification on your scope.

[asmi]

Also double check that you assign right color channels to HDMI data lanes, as they are not interchangeable. Data lane 0 is for blue color data and sync signals, lane 1 - green, lane 2 - red.

[BrianHG]

Also double check that you assign right color channels to HDMI data lanes, as they are not interchangeable. Data lane 0 is for blue color data and sync signals, lane 1 - green, lane 2 - red.

He's still missing something so much more simple stupid.  I want to see if he can figure it out....

[nockieboy]

Also double check that you assign right color channels to HDMI data lanes, as they are not interchangeable. Data lane 0 is for blue color data and sync signals, lane 1 - green, lane 2 - red.

He's still missing something so much more simple stupid.  I want to see if he can figure it out....

I haven't got DE or DDC_EN outputs set up. DE needs to be LOW, DDC_EN needs to be HIGH.

[BrianHG]

Also double check that you assign right color channels to HDMI data lanes, as they are not interchangeable. Data lane 0 is for blue color data and sync signals, lane 1 - green, lane 2 - red.

He's still missing something so much more simple stupid.  I want to see if he can figure it out....

I haven't got DE or DDC_EN outputs set up. DE needs to be LOW, DDC_EN needs to be HIGH.

[nockieboy]

Silly-scope traces for clock p & n and data lane 0 p & n attached, showing 180-degree phase difference.

Despite adding the DE signal (permanently LOW), still no image on the monitor.  I'm going to need to do some further testing with the monitor (root out my old RPi with full-size HDMI connector on it) to make sure it's not the monitor messing me about (there's only one HDMI connector on the back, so no confusion over DVI/HDMI).

I guess I'm going to need to start thinking about somehow testing for signals coming out at the HDMI connector on the DVI tester?

[BrianHG]

Strange, usually the pixel clock is the lowest frequency component.
The other data lines should have components averaging to the middle of your low bandwidth scope since they are operating in the 125MHz domain...

Also, channels 0,1 & 2 may be backwards.

[asmi]

Silly-scope traces for clock p & n and data lane 0 p & n attached, showing 180-degree phase difference.

Is horizontal scale the same on both traces? If so, your clock is wrong - HDMI clock lane is a symbol clock, not pixel one. As such, one period of symbol clock should cover 10 bit times for the data lanes.

[BrianHG]

Silly-scope traces for clock p & n and data lane 0 p & n attached, showing 180-degree phase difference.

Is horizontal scale the same on both traces? If so, your clock is wrong - HDMI clock lane is a symbol clock, not pixel one. As such, one period of symbol clock should cover 10 bit times for the data lanes.

This is a bit of a problem as his scope is 20MHz only and we cannot predict what the output and trace lock & would look like on the lanes.  Especially with a fixed test pattern.  I would have foreseen more middle level junk.  Perhaps in the horizontal frame, there just seems to be a repetitious pattern which appears to be lower frequency than the pixel clock.  In the simulation output, the data lanes do have 10 distinct bits per 'symbol clock'.  And the symbol clock does end up being equal to what would be the equivilant VGA dac pixel clock in the end.

[BrianHG]

@Nockieboy, with the 'IO Standard' set to LVDS_E_3R, you probably need to add those 8x 51ohm resistors to your DVI tester board.  However, I only see this as an issue above 300mbps.

[BrianHG]

You have been Nockied!!!



I wonder how long this would have gone on if I hadn't checked...

[nockieboy]

   I'll get my coat...

All the outputs need to be reversed on the Quartus schematic - so that means the clock is the one pair that now doesn't need to be reversed...?

EDIT:  In my defence, the TX outputs where connected up to the PTN3366 to create the simplest routing to the HDMI connector.  If I'd connected positive to positive, negative to negative, each of the pairs would have had to cross over to get to the HDMI connector...  Which seems a bit odd, you'd think the chip or the connector would be made so that wouldn't happen, but I recall someone telling me a while ago that it didn't matter which way round the connections were made, but I guess it helps to know that they're swapped around though, so that the outputs can be swapped accordingly in Quartus...  I'd forgotten I'd done that.

[nockieboy]

I just want to confirm that reversing the outputs is simply a case of swapping the output as per the attached schematic?

[BrianHG]

Yes, in Quartus, move the clk pin back to the positive output from the module and move the 3 data lines to the module's negative output...
You got it right.

[nockieboy]

Apologies for the potato-camera picture, but IT WORKS!! 



Bit blurry, but the screen boundaries are clearly visible and the monitor is picking up a 480p/60Hz HDMI signal.

EDIT: Not shown in the picture above, but I stepped through the monitor's menu and it was also picking up the audio component in the HDMI signal - although there's no sound to hear just yet.

[BrianHG]

Ready to try 720 @ 60Hz?
Also, 1080p @ 30Hz?  (No blur on this one...)

Also, a 2.5v IO test...  Though, that NXP amplifier IC was explicit, it should work from 2.5v drive all the way to 0.325v drive.

[nockieboy]

Ready to try 720 @ 60Hz?
Also, 1080p @ 30Hz?  (No blur on this one...)

Definitely.  I'm just looking through the code currently to see how to set it up for 720p.

[BrianHG]

Bit blurry, but the screen boundaries are clearly visible and the monitor is picking up a 480p/60Hz HDMI signal.

Yes, unlike analog VGA where the monitor may add artificial sharpness for the quality of the ADC sampling and poor analog cables, the full digital DVI/HDMI upsampling usually looks smoother/softer...

[BrianHG]

Oooops, the module you are using uses x10 on the PLL instead of x5.  I don't think they are using Altera's SERDES.  If not, it may not be possible to achieve the 742.5mbps as the code cant run that fast if they are using a software SERDES instead of a hardware one.

The code internally seems to support DDRIO mode, IE shift 2 bits per clock.  You will need to read up on how to get it to work, or it might be automatic...

[nockieboy]

Bit blurry, but the screen boundaries are clearly visible and the monitor is picking up a 480p/60Hz HDMI signal.

Yes, unlike analog VGA where the monitor may add artificial sharpness for the quality of the ADC sampling and poor analog cables, the full digital DVI/HDMI upsampling usually looks smoother/softer...

Oh it was sharp enough irl, it's just my mobile camera was having trouble with the lighting in the room and my hands weren't steady enough to take a sharp picture.