I wasn't aware Micron had HDL simulation models. That's great. Do you guys know of any other vendor that does?
And stupid me, I created a module called : BrianHG_DDR3_GEN_tCK.sv
Which synthesizes all the data sheet's timing t## clock cycles based on ram chip selection in one of the main parameters. However, Micron's own model Verilog code also has these 4 source codes:
1024Mb_ddr3_parameters.vh
2048Mb_ddr3_parameters.vh
4096Mb_ddr3_parameters.vh
8192Mb_ddr3_parameters.vh
Which almost does the same thing. Though, mine 1 for all ram sizes including 512MB DDR3, and is also synthesizes the MRS MR# registers based on a few inputs to select the function state of the memory. Mircon's ddr3.v verifies that these have been setup properly when I run the MRS commands. Example:
#
# Note : Cyclone IV E PLL locked to incoming clock
# Time: 2670000.0 ps Instance: BrianHG_DDR3_PHY_SEQ_tb.DUT_DDR3_PLL.genblk3.HPLL1.cycloneiii_pll.pll3
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.reset at time 2690000.0 ps WARNING: 200 us is required before RST_N goes inactive.
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.reset: at time 2690000.0 ps ERROR: CKE must be inactive when RST_N goes inactive.
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.reset: at time 2690000.0 ps ERROR: CKE must be maintained inactive for 10 ns before RST_N goes inactive.
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task at time 2691000.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active.
#
#
# MR0 Settings:
# M[12] - Precharge PD = 1 = DLL On.
# M[11:9] - Write Recovery = 1 = 5.
# M[8] - DLL Reset = 0 = No.
# M[6,5,4,2] - CAS# Latency = 001,0 = 5.
# M[3] - BT Read Burst Type = 0 = Sequential (nibble).
# M[1:0] - BL Burst Length = 00 = Fixed BL8.
#
#
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3213000.0 ps INFO: Load Mode 0
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3213000.0 ps INFO: Load Mode 0 Burst Length = 8
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3213000.0 ps INFO: Load Mode 0 Burst Order = Sequential
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3213000.0 ps INFO: Load Mode 0 CAS Latency = 5
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3213000.0 ps INFO: Load Mode 0 DLL Reset = Normal
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3213000.0 ps INFO: Load Mode 0 Write Recovery = 5
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3213000.0 ps INFO: Load Mode 0 Power Down Mode = DLL on
#
#
# MR1 Settings:
# M[12] - Q Off = 0 = Enabled.
# M[11] - TDQS = 0 = Disabled.
# M[9,6,2] - Rtt = 0,1,0 = RZQ/2 (120 Ohm [NOM]) | RZQ/2 (120 Ohm [NOM])
# M[7] - Write Levelization = 0 = Disable (normal).
# M[4:3] - Additive Latency (AL) = 00 = Disabled (AL = 0).
# M[5,1] - Output Drive Strength = 0,0 = RZQ/6 (40 Ohm [NOM]).
# M[0] - Dll Enabke = 0 = Enable (normal).
#
#
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3239000.0 ps INFO: Load Mode 1
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3239000.0 ps INFO: Load Mode 1 DLL Enable = Enabled
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3239000.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3239000.0 ps INFO: Load Mode 1 ODT Rtt = 120 Ohm
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3239000.0 ps INFO: Load Mode 1 Additive Latency = 0
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3239000.0 ps INFO: Load Mode 1 Write Levelization = Disabled
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3239000.0 ps INFO: Load Mode 1 TDQS Enable = Disabled
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3239000.0 ps INFO: Load Mode 1 Qoff = Enabled
#
#
# MR2 Settings:
# M[10:9] - Dynamic ODT (Rtt(WR)) = 2 = RZQ/2 (120 Ohm [NOM]).
# M[7] - Self Refresh Temperature = 0 = Normal (0c to 85c).
# M[5] - Auto Self Refresh (Optional) = 0 = Disabled: Manual.
# M[5:3] - CAS Write Latency (CWL) = 0 = 5 CK (tCK >= 2.5ns).
#
#
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3265000.0 ps INFO: Load Mode 2
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3265000.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3265000.0 ps INFO: Load Mode 2 CAS Write Latency = 5
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3265000.0 ps INFO: Load Mode 2 Auto Self Refresh = Disabled
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3265000.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3265000.0 ps INFO: Load Mode 2 Dynamic ODT Rtt = 120 Ohm
#
#
# MR3 Settings:
# M[2] - Multipurpose Register MPR = 0 = Normal DRAM Operations.
# M[1:0] - MPR_RF = 0 = Predefined Pattern.
#
#
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3291000.0 ps INFO: Load Mode 3
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3291000.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3291000.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3355000.0 ps INFO: Refresh
#
# End of command source ASCII file 'DDR3_SEQ_CMD_script.txt'.
# 79 lines processed.
#
# ** Note: $stop : BrianHG_DDR3_PHY_SEQ_tb.sv(275)
# Time: 3850 ns Iteration: 1 Instance: /BrianHG_DDR3_PHY_SEQ_tb
The nicely spaced MR descriptions & settings are executed and sent out to the DDR3 bus by my code and reverse decoded by my code while the ugly:
# BrianHG_DDR3_PHY_SEQ_tb.sdramddr3_0.cmd_task: at time 3355000.0 ps INFO: *******
Is what the Micron ddr3.v model is reporting how a DDR3 ram chip is functioning. As you can see at the top, the errors say I need to clean up my power-up and reset sequence.