FPGA VGA Controller for 8-bit computer

[asmi]

Also, free IP blocks are very important (Quartus seems to have less free IP) when one want to make use of the board for anything other than learning.  For example, nobody writes a DDR3 controller or a network stack, but uses available IP blocks instead.  If these blocks are not free to use, than they are certainly too expensive for hobby projects anyway, so it is very important to have them for free in the toolchain.  If we consider the free part of the software toolchain, then the Zynq become even more attractive.  I didn't really work with Quartus/Nios, but from reading the specs so far it seems Vivado has more free goodies and will be more productive for projects.

I'm sure folks from this thread will get a good laugh reading this, as I've been trying to convince them to switch to Xilinx FPGA pretty much entire time this thread exists

Same with Linux, very important not for exercising shell commands, but because it will allow access to all the drivers and tools and applications already existing for Linux.

What utility does it have with chip that's got only 25K gates?

I won't try to convince you any further about the value of that Zynq board, not trying to sell anything.   

And yet you're still trying  I don't see the value of Zynq itself. I have a bunch of Zynq-030 chips which I snagged for cheap, but I'm yet to come up with an application for it.

I would also rather buy the Altera board, same as you, just that for different reasons (e.g. has a MIPI connector, or the two SMA for the ADC, good to improvise a DAQ if it only were a free Linux for it, and it seems it is one, but I'm too new to this board+toolchain to disseminate between facts and marketing hype).  In fact the only thing that kept me not to buy one yet was that I don't know what IP blocks are free for Quartus/Nios II.

What's with this attempts to shove Linux everywhere? You don't need it for most embedded projects. As a matter of fact, I've never had to use it in any of my FPGA projects, commercial or not.

[nockieboy]

I'm sure folks from this thread will get a good laugh reading this, as I've been trying to convince them to switch to Xilinx FPGA pretty much entire time this thread exists

Just so we're clear, I'm using Altera FPGAs because that's what the resident expert (BrianHG) is most familiar with and without whom this project would still be stuck at the 'coloured bars' stage.

What's with this attempts to shove Linux everywhere? You don't need it for most embedded projects. As a matter of fact, I've never had to use it in any of my FPGA projects, commercial or not.

This may not be a popular opinion, but I have to say that I absolutely HATE Linux with a passion normally reserved for genocidal maniacs and parking wardens.  It always seems to me that if there is a more convoluted way of doing things, Linux will make you do it.

In other news, looks like my USB interface is going to work (just need to set up and test the SPI interface), so I'll be scrubbing the PS/2 interface from the CV PCB to make some more room - maybe for another USB interface so I can use mouse and keyboard at the same time. 

If anyone was following along with the USB developments (I haven't really been updating the forum with it, but have mentioned it a couple of times), I've decided to drop the MAX3421E as it was proving to be a bit of a headache to get working with the FPGA - instead I'm using a SAMD21G microcontroller instead.  It's actually cheaper (I can buy two SAMD21Gs for one MAX3421E) and can send data to the FPGA via SPI, I2C or serial, so it makes the whole thing a lot simpler (at least for me anyway).  Yes, they're overpowered for the application, but then so is the FPGA. 

[BrianHG]

So, whats going on...
There are years of work ahead of us...
Changes to be made...
Swaps to new hardware...
New things to implement...

[nockieboy]

Everything else shouldn't be wired.  The DDR3 gets absolute priority, then you can think about everything else.

I do have some physical constraints with the board layout that I have to consider.  How much impact they have on the design is up for grabs, but there's the power supplies around the board, 26 address signals from the left side of the board, 18 data and control signals from the right side, SD (which I'm putting on the underside of the PCB) and audio jack at the top and DVI/HDMI, USB/PS2 need to be at the bottom.  Other than rotating the FPGA and shunting the modules whose position is only limited to one side of the PCB around, there's not a lot else I can do. (Purple areas are power supplies).

Please check Cyclone V Device Handbook: Volume 1: Device Interfaces and Integration, page 216, Figure 6-8: PHYCLK Networks in Cyclone V E A2 and A4 Devices to show you the PLL connection to the banks.  You want to select IO banks which share a PLL and whose PLL has a dedicated outputs directly to one of the bank.  Make sure that your reference clock oscillator input is on a positive clock pin which goes to that PLL.  Page 206/207 shows the connections to the DQS groups and which shared DLL have direct connections.

Banks 1 & 2 are fed solely by the left PLL and banks 5 & 6 are fed by the right PLL.  All other banks have access to both PLLs.  But you've said not to use bank 5A, so that writes off the right hand side.  Bank 1 doesn't seem to exist and the rest of the left hand side (bank 2A) has 10 DQ and 2 DQS IOs.

Banks 7 & 8 seem to be the best option as they have 32 IOs between them, plenty of DQ and DQS pins, the reference clock feeds into bank 7A and the only disruption to existing connections would be to the auxiliary equipment on the top edge of the board (SD card, audio output, PC serial and debug serial, LEDs) - none of which would suffer from longer traces to other parts of the FPGA or being relocated somewhere else on the PCB entirely (except for audio).

Unless the fact it would take a PLL out of the equation for one other side of the FPGA would be an issue?

Do you agree?

I think you might have missed my last post with the discussion on dev boards. 

[BrianHG]

Yes, 7&8 look good.
Remember, The 2 DQS (DQS&DQSn) in 7 and 8 go to the ram's UDQS and LDQS, while the bank with the bank wired to the UDQS gets the high word DQ bits [15:8] while the bank wired to the LDQS gets the [7:0] DQ bits.  When selecting the dedicated PLL output clock pins, make sure that same PLL also reaches your third IO bank where you will have the bulk of addressees and ram controls.  If a third bank is needed, it will probably be bank 5B.

Don't discount that dev board.  I know we can get 3 CV at 19$ (inflation) from LCSC, but, that's all for who knows how long.  I haven't played with Lattice (but I did install it), but, If it is possible to port the design over to their FPGA, the 45k gate LFE5U device is in mass production and it is 16$ at digikey, mouser, and future electronics.  For a public domain project, availability and price may be a plus.  Your current CV is 25k gate, 35$ at mouser and it is not guaranteed that it can be tricked into it's 50k gate equivilant.

[nockieboy]

Don't discount that dev board.  I know we can get 3 CV at 19$ (inflation) from LCSC, but, that's all for who knows how long.  I haven't played with Lattice (but I did install it), but, If it is possible to port the design over to their FPGA, the 45k gate LFE5U device is in mass production and it is 16$ at digikey, mouser, and future electronics.  For a public domain project, availability and price may be a plus.  Your current CV is 25k gate, 35$ at mouser and it is not guaranteed that it can be tricked into it's 50k gate equivilant.

I've no aversion to swapping to a better FPGA if you are happy to - I'm totally guided by the support I can receive on a particular FPGA family and am not experienced enough with this stuff to have any particular preference (other than being familiar with Cyclones now).  asmi has been singing the virtues of Xilinx for months now and if he's happy to help out where he can, perhaps it's not such a bad idea. Naturally, there'd be a huge learning curve for me with the tool chain etc, but maybe it's time to address that elephant in the room?

[SMB784]

Don't discount that dev board.  I know we can get 3 CV at 19$ (inflation) from LCSC, but, that's all for who knows how long.  I haven't played with Lattice (but I did install it), but, If it is possible to port the design over to their FPGA, the 45k gate LFE5U device is in mass production and it is 16$ at digikey, mouser, and future electronics.  For a public domain project, availability and price may be a plus.  Your current CV is 25k gate, 35$ at mouser and it is not guaranteed that it can be tricked into it's 50k gate equivilant.

I've no aversion to swapping to a better FPGA if you are happy to - I'm totally guided by the support I can receive on a particular FPGA family and am not experienced enough with this stuff to have any particular preference (other than being familiar with Cyclones now).  asmi has been singing the virtues of Xilinx for months now and if he's happy to help out where he can, perhaps it's not such a bad idea. Naturally, there'd be a huge learning curve for me with the tool chain etc, but maybe it's time to address that elephant in the room?

Having worked with both Altera & Xilinx toolchains, I can honestly say the difference is not that substantial in terms of user interface.  The design flow is the same, and the buttons for the various workflow stages are even mostly in the same place.

The benefit I see with Vivado over Quartus Prime is that the simulation suite is built into the main design IDE, not separate from it like Modelsim.  I think you overestimate the learning curve between the two.  It took me less than a week to get a fair mastery of Vivado after only working with Quartus.

[BrianHG]

Don't discount that dev board.  I know we can get 3 CV at 19$ (inflation) from LCSC, but, that's all for who knows how long.  I haven't played with Lattice (but I did install it), but, If it is possible to port the design over to their FPGA, the 45k gate LFE5U device is in mass production and it is 16$ at digikey, mouser, and future electronics.  For a public domain project, availability and price may be a plus.  Your current CV is 25k gate, 35$ at mouser and it is not guaranteed that it can be tricked into it's 50k gate equivilant.

I've no aversion to swapping to a better FPGA if you are happy to - I'm totally guided by the support I can receive on a particular FPGA family and am not experienced enough with this stuff to have any particular preference (other than being familiar with Cyclones now).  asmi has been singing the virtues of Xilinx for months now and if he's happy to help out where he can, perhaps it's not such a bad idea. Naturally, there'd be a huge learning curve for me with the tool chain etc, but maybe it's time to address that elephant in the room?

My concern is $ per K gate & availability.  I'd like to make code which runs on all 3 platforms like almost all of your current core code.
In Xilinx, how much does a ~45k gate, ~2 megabit part cost?

Right now, the CV 25k gate 5CEBA2F17C8N is 34.81$ at Mouser and it may be hack-able to the 50k gate 5CEBA4F17C8N which costs 50$.  LCSC has the 5CEBA2 at 19$, but they do not seem to have many unless you back order.

The lattice part is also a 256 pin BGA @ 15.86$.  It is a hair faster than the CV.  The lattice 25k gate variant isn't worth it as it is 9.29$.  Might as well pay the additional 6$ for double the size. The lattice LFE5U-85F-6MG285C is 30$ (finer 285 pin BGA which may be difficult for beginners and PCB price for finer pitch layout), that's 85k gate and 4 megabit for less than the 25k gate CV price.  These prices are to buy 1 at a time.

~25k gate will allow you to do almost everything under the sun fine.  ~45k gate will allow you to do it all and have breathing room.  Your Achilles heel would then be that limiting 256 pins unless you shove the Z80 CPU inside the FPGA or multiplex / IO expand the IO ports with 3 wire serial to parallel interface IO ICs which can also do the TTL conversion for you.

The 50k gate dev board while available is a fluke deal as it has a 50k gate, 484 pin 125$ FPGA on it.  However, this deal will soon end & you cannot expect anyone else out there to pay 100$ for a FPGA for a Z80.

[BrianHG]

The benefit I see with Vivado over Quartus Prime is that the simulation suite is built into the main design IDE, not separate from it like Modelsim.  I think you overestimate the learning curve between the two.  It took me less than a week to get a fair mastery of Vivado after only working with Quartus.

We have still yet to see anyone run my simulation code of the geometry unit on the previous page in Xilinx.  It has no altera dependencies and the way it is setup and I did post the compile time and execution time for 2 key scripts to be executed.  It would be nice to know if Xilinx can do the 13,851,400 ns runtime sim, 1,385,140 CLK cycles, in a reasonable amount of time and properly render / generate the .bmp picture.
https://www.eevblog.com/forum/fpga/fpga-vga-controller-for-8-bit-computer/msg3456782/#msg3456782
https://www.eevblog.com/forum/fpga/fpga-vga-controller-for-8-bit-computer/msg3447916/#msg3447916


If we are going to jump FPGA vendors, the most valuable choice here is $/k-gate as our code isn't too complex as it currently fits on a 10kgate chip and we only expect it to double it's current size.  Though, I would like whatever vendor we choose support IEEE754 floating point natively as Altera currently does.  We can add some nice geometry pre-processing so we can simulate all the functions of an analog vector graphics display including true rotation as well as provide a FPU for the Z80.  Though, recently I found on opencores a compact 2-3 clock cycle -29 to +24 exponent FPU, with 17 clock cycle divide which can operate on all vendors while the full -128 to +127 exponent unit exists, but has a huge pipeline penalty.

[RoGeorge]

Once I've designed a Z80 computer, it was made to be compatible with CP/M (to benefit from the software tools available for CP/M) and ZX Spectrum (for games). It was all on a single big perfboard.  Please allow me to show off, 'cause it's weekend! 







https://hackaday.io/project/1411-xor-hobby-a-vintage-z80-computer-prototype

Thought the output was for a TV back then.  The RAM chips were normal dynamic memories 16384 x 1bit (normal as in not dual port), double addressed by the processor and by the video controller using address demultiplexers, a few counters and some glue logic to carefully pause the Z80 clock to avoid memory accessing conflicts.

The control logic to implement that was roughly 30 TTL chips, and about 100 chips all together with the floppy disk interface, the RAM chips, EPROMs, buffers, processor, etc.

- 1. I don't understand, why a less than 50kLE FPGA would be a problem.  My guesstimation is that that amount should be enough for a video adapter, including a softcore Z80, too.  The original Z80 was less than 10 000 transistors, so I expect a Z80 IP to fit in less than 10 kLE, but never tested one, how big is the Z80 IP?  Why would, let's say a 20kLE, not be enough?

- 2. Why adding a whole VGA?  Wouldn't be easier to just control a HDMI chip (or alike), so to get video output without trying to align to the VGA standard?  Were there any Z80 computer with VGA back in the days?

- 3. Will this Z80 try to be compatible with certain computer models, so it can run old Z80 games and software?

- 4. For the questions in the OP, that missing website has many snapshots on the WaybackMachine Internet archive:
https://web.archive.org/web/20190713224608/http://searle.hostei.com/grant/z80/SimpleZ80.html

- 5. My guess is the request from the OP has changed during the last ~100 pages of replies, can anybody make a short brief (2-3 phrases) of the current project, please?

Not trying to argue about what FPGA to use or anything alike, just curious about the current goal and status of the project.

[asmi]

We have still yet to see anyone run my simulation code of the geometry unit on the previous page in Xilinx. 

I did try it, and it crashed Vivado's builtin sim while parsing GPU_GEO_tb. I couldn't really figure out why in the time I had for this, but it seems like it's related to handling unpacked arrays vs packed vectors. That module is just way too large for me to go in and try fixing it, without breaking anything in a process.
Since there is no top level module, I didn't try running synthesis to see if that would work.
Vivado IDE supports integration with other simulators (including ModelSim), so if the issue is with simulator, that can be worked around.

If we are going to jump FPGA vendors, the most valuable choice here is $/k-gate as our code isn't too complex as it currently fits on a 10kgate chip and we only expect it to double it's current size.  Though, I would like whatever vendor we choose support IEEE754 floating point natively as Altera currently does.  We can add some nice geometry pre-processing so we can simulate all the functions of an analog vector graphics display including true rotation as well as provide a FPU for the Z80.  Though, recently I found on opencores a compact 2-3 clock cycle -29 to +24 exponent FPU, with 17 clock cycle divide which can operate on all vendors while the full -128 to +127 exponent unit exists, but has a huge pipeline penalty.

I disagree that gates per $ is the most important metric. To me it's actually not even in the top 3, the most important metrics are almost always raw performance and IO features (how many and how fast transceivers I need, how many IO and their configuration, which has implications to the kind of memory layouts I can implement). But I'm not the one making decisions here, so what do I know
As for Z80 softcore, why not design your own? This project is about learning right? I definitely learnt a lot as I was working on my own softcores, so I think this is a good project for learning.
That said, I still use Microblaze softcore in all of my "serious" FPGA designs, because - convenience. It's already there, completely free of charge, you can configure it however your want, there is a ready-to-go software toolchain with live visual debugging support, there are a ton of support libraries and drivers for different peripherals, you can even run Linux on it if you so desire. So as long as the focus of my project is not an actual softcore, using MB is really a no-brainer.

[nockieboy]

Once I've designed a Z80 computer, it was made to be compatible with CP/M (to benefit from the software tools available for CP/M) and ZX Spectrum (for games). It was all on a single big perfboard.  Please allow me to show off, 'cause it's weekend! 

Wow - that's some wiring spaghetti!   I started out on a breadboard, then moved to DIP soldering on PCBs and am now plummeting down the SMD rabbit hole into Wonderland, it seems.  Or at least BGA territory.  I wanted to see if I could build something more powerful than my first computer - one of these - and it seems I've done that in spades, with the video output being the final hurdle.

- 1. I don't understand, why a less than 50kLE FPGA would be a problem.  My guesstimation is that that amount should be enough for a video adapter, including a softcore Z80, too.  The original Z80 was less than 10 000 transistors, so I expect a Z80 IP to fit in less than 10 kLE, but never tested one, how big is the Z80 IP?  Why would, let's say a 20kLE, not be enough?

We've filled a 10kLE FPGA and there's still more we could do with the GPU, let alone all the other bits.  I want to add an AY-8910 PSG into the FPGA as well, because that's what my first computer had and I like chiptunes.   I'll probably end up adding a better, more capable PSG (Programmable Sound Generator) too.  Of course, there's always the possibility of putting a softcore Z80 into the FPGA too with the room we have, but that's not really my goal.

- 2. Why adding a whole VGA?  Wouldn't be easier to just control a HDMI chip (or alike), so to get video output without trying to align to the VGA standard?  Were there any Z80 computer with VGA back in the days?

We started with VGA as I knew nothing about it and it was the easiest introduction to video output.  As you've missed most of the last year's worth of thread, it's important that you understand that I'm not a professional programmer and my experience with electronics started with the project to build my DIY computer two years ago (nearly three now!)  I didn't really know what an FPGA was until I started this thread, my soldering skills extended to the SOIC chip and even that scared me!  I'm trying to learn all this on the fly, as it were.  Sometimes things stick and I get them straight away, sometimes BrianHG and everyone else on the forum have to put up with me being really thick and not getting something until it's repeated fifteen times, in fifteen different ways. 

- 3. Will this Z80 try to be compatible with certain computer models, so it can run old Z80 games and software?

It runs CP/M 2.2 and CP/M 3, but it's not designed to be compatible with any particular old computer, it's just designed to be as simple as possible (until this thread started!)  This GPU project is by far the most complicated and modern part of it.  Whilst I'm designing a video card for my computer, we're also making it open source so that anyone building their own computer (be that Z80-based, 680x0-based, or Intel 4004-based) can use the HDL in their project.

- 4. For the questions in the OP, that missing website has many snapshots on the WaybackMachine Internet archive:
https://web.archive.org/web/20190713224608/http://searle.hostei.com/grant/z80/SimpleZ80.html

Yep, that was answered over a year ago - but thanks.   Grant Searle opened up another website after he had issues with the internet provider for the one that went down.

- 5. My guess is the request from the OP has changed during the last ~100 pages of replies, can anybody make a short brief (2-3 phrases) of the current project, please?

Well, I've pretty-much outlined most of the brief above, but basically I had a cheap Cyclone II FPGA board and was trying to find out what all this 'FPGA' stuff was about and see if I could build the FPGA computer from Grant Searle's website, my intention being to just use the VGA HDL to create a video card for my computer.

The thread quickly turned into an education on designing and building a VGA card using a Cyclone IV FPGA, which I did and it works wonderfully.  We pushed on from there after I asked a question about how would graphics acceleration work and now the GPU can draw lines, rectangles, quads, triangles, circles and arcs at rates my old computer couldn't even dream of.  It also has a PS/2 port for a keyboard and my little computer is completely standalone now.

We're at the stage now where I'm designing a 'version 2' of the GPU card, using a bigger FPGA to accommodate more features, with full HDMI output, proper audio output (the 1st version has a buzzer), SD card (hopefully to replace the CF card interface I created for my computer) and replacing the PS/2 port with a USB port so I can use modern keyboards, maybe a mouse, plus DDR3 RAM for even more graphics memory.

[iMo]

- 1. I don't understand, why a less than 50kLE FPGA would be a problem.  My guesstimation is that that amount should be enough for a video adapter, including a softcore Z80, too.  The original Z80 was less than 10 000 transistors, so I expect a Z80 IP to fit in less than 10 kLE, but never tested one, how big is the Z80 IP?  Why would, let's say a 20kLE, not be enough?

Complete ZX Spectrum (incl. Z80 cpu, ula and video ram) fits into 3700 LEs (and 131kbits of internal ram) of a Cyclone II..

..That said, I still use Microblaze softcore in all of my "serious" FPGA designs, because - convenience. It's already there, completely free of charge, you can configure it however your want, there is a ready-to-go software toolchain with live visual debugging support, there are a ton of support libraries and drivers for different peripherals, you can even run Linux on it if you so desire. So as long as the focus of my project is not an actual softcore, using MB is really a no-brainer.

Long time back I ran some C code in order to compare MB (Spartan6) and pic32MX (because of their arch similarity) and got identical results. I doubt you can come with something "performing much better" than the MB..

[BrianHG]

I disagree that gates per $ is the most important metric. To me it's actually not even in the top 3, the most important metrics are almost always raw performance and IO features (how many and how fast transceivers I need, how many IO and their configuration, which has implications to the kind of memory layouts I can implement). But I'm not the one making decisions here, so what do I know

These metrics have already been reached with the cheapest FPGA for a Z80 or even interfacing with a 16 bit 68k.
The size just means play room to make any code we like.
A lot of our gates are eaten up by the unusual layering system which allows multiple color depths at multiple resolutions which optional multiple tiles all to be superimposed.  I guess we could have gone cheap with a fixed small 64 16x16 sprites plus 1 or 2 background layers.
The only plus to having true 1.5gbit serial out for true 1080p at 60hz.  For now, 720p@60 and 1080p@30 is fine.

However, to add a simple 3D accelerator to the core, 25k gates wont cut it.  45k gates will.
Yes, it would be nice to have 800mhz ram with a 1.6gtps bus, (unfortunately we would want even double that for 1080p@60) or faster, but we want to do all of this with an under 20$ fpga.

[asmi]

Yes, it would be nice to have 800mhz ram with a 1.6gtps bus, (unfortunately we would want even double that for 1080p@60) or faster, but we want to do all of this with an under 20$ fpga.

Where did that requirement came from? The kind of FPGA you can get for $20 (from official sources) is pretty useless.

[BrianHG]

We have still yet to see anyone run my simulation code of the geometry unit on the previous page in Xilinx. 

I did try it, and it crashed Vivado's builtin sim while parsing GPU_GEO_tb. I couldn't really figure out why in the time I had for this, but it seems like it's related to handling unpacked arrays vs packed vectors. That module is just way too large for me to go in and try fixing it, without breaking anything in a process.

No warnings, just plain up crash? 
If I ever go to Xilinx, this is the first thing I would post on their troubleshooting site...
This code does sim to work on ModelSim 10.1 through 20.1.  I only wish modelsim had a better integrated text editor, guess I got to use an external one.

[nockieboy]

My concern is $ per K gate & availability.  I'd like to make code which runs on all 3 platforms like almost all of your current core code.
In Xilinx, how much does a ~45k gate, ~2 megabit part cost?

Right now, the CV 25k gate 5CEBA2F17C8N is 34.81$ at Mouser and it may be hack-able to the 50k gate 5CEBA4F17C8N which costs 50$.  LCSC has the 5CEBA2 at 19$, but they do not seem to have many unless you back order.

The lattice part is also a 256 pin BGA @ 15.86$.  It is a hair faster than the CV.  The lattice 25k gate variant isn't worth it as it is 9.29$.  Might as well pay the additional 6$ for double the size. The lattice LFE5U-85F-6MG285C is 30$ (finer 285 pin BGA which may be difficult for beginners and PCB price for finer pitch layout), that's 85k gate and 4 megabit for less than the 25k gate CV price.  These prices are to buy 1 at a time.

I seem to recall the Lattice Diamond software licensing put me off - I've just had a check on the Lattice website, and the free version of Diamond doesn't do SERDES-based Lattice FPGAs.  In fact, it doesn't support ECP5UM, ECP5UM5G, LatticeECP3, LatticeECP2M/S, LatticeECP2/S, LatticeSC or LatticeSCM.  Don't we need SERDES for the HDMI output?

Yes, it would be nice to have 800mhz ram with a 1.6gtps bus, (unfortunately we would want even double that for 1080p@60) or faster, but we want to do all of this with an under 20$ fpga.

Where did that requirement came from? The kind of FPGA you can get for $20 (from official sources) is pretty useless.

Well, the cheaper the better obviously.  My biggest concern regarding the cost of the FPGA so far has been my ability to solder one to a PCB, closely followed by my ability to design a PCB that it can work on.  I don't want to waste too much money learning to solder BGAs and I don't want to bulk-buy SMD-assembled boards as the PCB design I'm using is specific to my single use-case.  I only really need one or two at most.  Anyone else making use of this project will be doing so for their own project which likely won't match my layout at all.

[BrianHG]

Yes, it would be nice to have 800mhz ram with a 1.6gtps bus, (unfortunately we would want even double that for 1080p@60) or faster, but we want to do all of this with an under 20$ fpga.

Where did that requirement came from? The kind of FPGA you can get for $20 (from official sources) is pretty useless.

Nockieboy did not want to pay more than 20$ for an FPGA.
Lattice is good with density and price.  And this is from official sources.

[asmi]

No warnings, jut plain up crash? 

It said something like access violation, and a long C++ stack trace, so it's definitely internal error.

If I ever go to Xilinx, this is the first thing I would post on their troubleshooting site...

I plan to do that, but I will need to invest some time into seeing what exactly is causing an issue. I doubt their devs would be thrilled to decipher 1.3 kloc to see what is wrong over there. I know I wouldn't.

This code does sim to work on ModelSim 10.1 through 20.1.  I only wish modelsim had a better integrated text editor, guess I got to use an external one.

I use VS code with plugin for SystemVerilog, it's far superior to anything else out there in my opinion.

[asmi]

Well, the cheaper the better obviously.  My biggest concern regarding the cost of the FPGA so far has been my ability to solder one to a PCB, closely followed by my ability to design a PCB that it can work on.  I don't want to waste too much money learning to solder BGAs and I don't want to bulk-buy SMD-assembled boards as the PCB design I'm using is specific to my single use-case.  I only really need one or two at most.  Anyone else making use of this project will be doing so for their own project which likely won't match my layout at all.

One thing I like about Artix is that almost entire lineup is available in the same BGA256 package, so you can move up or down as you require without changing anything on a PCB. This package covers the range from 15T all the way up to 100T, with prices from ~27$ to ~$150 on Digikey. This allows using smaller part for the first board (so that you can verify the PCB works without risking too much money) before investing into larger device for the actual project.

[BrianHG]

My concern is $ per K gate & availability.  I'd like to make code which runs on all 3 platforms like almost all of your current core code.
In Xilinx, how much does a ~45k gate, ~2 megabit part cost?

Right now, the CV 25k gate 5CEBA2F17C8N is 34.81$ at Mouser and it may be hack-able to the 50k gate 5CEBA4F17C8N which costs 50$.  LCSC has the 5CEBA2 at 19$, but they do not seem to have many unless you back order.

The lattice part is also a 256 pin BGA @ 15.86$.  It is a hair faster than the CV.  The lattice 25k gate variant isn't worth it as it is 9.29$.  Might as well pay the additional 6$ for double the size. The lattice LFE5U-85F-6MG285C is 30$ (finer 285 pin BGA which may be difficult for beginners and PCB price for finer pitch layout), that's 85k gate and 4 megabit for less than the 25k gate CV price.  These prices are to buy 1 at a time.

I seem to recall the Lattice Diamond software licensing put me off - I've just had a check on the Lattice website, and the free version of Diamond doesn't do SERDES-based Lattice FPGAs.  In fact, it doesn't support ECP5UM, ECP5UM5G, LatticeECP3, LatticeECP2M/S, LatticeECP2/S, LatticeSC or LatticeSCM.  Don't we need SERDES for the HDMI output?

That's for the dedicated hardware GBPS transceivers in the ECP5UM, ECP5UM5G, not the ECP5U-45 which we are using.  It is the same with Altera, you need the paid version of Quartus for the GBPS devices.  Right now, the altlvds_tx is actually just generating a software shift-register in DDR mode on a normal IO pins.  And since the IO pins are just about the same speed as the ones in the Cyclone series, you will get the same 720p.

Well, in the datasheet ECP5 -6=624mb -7=700mb, -8=800mb.  (smartly, the slowest one can handle DDR3's minimum 303MHz)
                      All Cyclone -8=640mb -7=740mb,  -6=840mb. on select IOs.
                                      -8=550mb -7=640mb, -6=640mb. on all IOs.  (This is why you need a -7 to officially run DDR3 meeting that 303MHz target, though, right now, we achieved 1080mb on a -8 550mb output.  I bet we would get nailed on bus-turn-around.  1080 was achieves in output only mode and we don't care about temperature skew drift.  IE, want to run DDR3 this fast, we need 1 extra clock delay between swapping from read to write and back as the tri-state might need extra time to release and engage.)

Now I am not saying to blindly build a lattice board.  I'm saying to take a look to see if a ECP5U eval board exists, don't yet buy, but then investigate if our code will work in lattice diamond and wont crash it's simulator.  If that looks ok, then a minimum ECP5U eval board would be useful to test our code with HDMI output, even if you have to wire your current HDMI tester by hand.

[BrianHG]

This code does sim to work on ModelSim 10.1 through 20.1.  I only wish modelsim had a better integrated text editor, guess I got to use an external one.

I use VS code with plugin for SystemVerilog, it's far superior to anything else out there in my opinion.

Thanks...

[RoGeorge]

now the GPU can draw lines, rectangles, quads, triangles, circles and arcs at rates my old computer couldn't even dream of.  It also has a PS/2 port for a keyboard and my little computer is completely standalone now.

We're at the stage now where I'm designing a 'version 2' of the GPU card, using a bigger FPGA to accommodate more features, with full HDMI output, proper audio output (the 1st version has a buzzer), SD card (hopefully to replace the CF card interface I created for my computer) and replacing the PS/2 port with a USB port so I can use modern keyboards, maybe a mouse, plus DDR3 RAM for even more graphics memory.

Wow, quite a journey already, indeed, great project!   

[nockieboy]

That's for the dedicated hardware GBPS transceivers in the ECP5UM, ECP5UM5G, not the ECP5U-45 which we are using.  It is the same with Altera, you need the paid version of Quartus for the GBPS devices.

Ahh, okay.    Still seems that there's very few low-end dev boards for the ECP5U, from the little research I've been able to do so far.  Also, this post has concerned me a little as it seems to imply that we'll have to develop the DDR3 controller ourselves.  Having said that, I guess we'll be doing that anyway if the design is going to be fully FPGA-agnostic.  Using proprietary IP is vendor-specific, so I guess we'll be avoiding anything like that.

Now I am not saying to blindly build a lattice board.  I'm saying to take a look to see if a ECP5U eval board exists, don't yet buy, but then investigate if our code will work in lattice diamond and wont crash it's simulator.  If that looks ok, then a minimum ECP5U eval board would be useful to test our code with HDMI output, even if you have to wire your current HDMI tester by hand.

Unless anyone can point me to a Lattice ECP5U dev/eval board for less than $50, looks like I could be designing one from scratch.

[BrianHG]

That's for the dedicated hardware GBPS transceivers in the ECP5UM, ECP5UM5G, not the ECP5U-45 which we are using.  It is the same with Altera, you need the paid version of Quartus for the GBPS devices.

Ahh, okay.    Still seems that there's very few low-end dev boards for the ECP5U, from the little research I've been able to do so far.  Also, this post has concerned me a little as it seems to imply that we'll have to develop the DDR3 controller ourselves.  Having said that, I guess we'll be doing that anyway if the design is going to be fully FPGA-agnostic.  Using proprietary IP is vendor-specific, so I guess we'll be avoiding anything like that.

Now I am not saying to blindly build a lattice board.  I'm saying to take a look to see if a ECP5U eval board exists, don't yet buy, but then investigate if our code will work in lattice diamond and wont crash it's simulator.  If that looks ok, then a minimum ECP5U eval board would be useful to test our code with HDMI output, even if you have to wire your current HDMI tester by hand.

Unless anyone can point me to a Lattice ECP5U dev/eval board for less than $50, looks like I could be designing one from scratch.

I know, lattice doesn't think like that, or are relying on the lower end Mach dev boards, or that the 99$ board with included programmer + including a limited time version their full compiler is good enough.

Yes, we are importing a public domain DDR3 controller, but for now, using Altera's binds you to the proper IO pins and generates for you an example .SDC file which sets-up the timing constraints for the IO pin, the 2 things missing in the public-domain controller.  As for the IO buffer, there's a standard DDR-DQS-BIDIR-IOBUF function port just like the altlvds_tx/rx which can be plugged into the DDR3.sv source file.  DDR3 is as simple to run as DDR2, DDR except for the different power-up settings and a few new commands and # of clock cycles.  Maybe a punishment for not writing your own HDMI transmitter would be writing your own DDR3.sv.  Micron does have a DDR3 Verilog testbench code which was designed to validate/verify functionality of your DDR3.sv controller which you can run in ModelSim.  Sorta like my testbench code which drives and tests the 3 Geometry unit sections wired together to render an output.