Your simulation doesn't seem to be doing anything at all.
In your test-bench, are you generating any signals, like a basic clock?
The sim should be counting up time in the status bar until you click stop, or your testbench code generates a $stop or $end.
This is what the key portion of my TB looks like:
localparam period = 500000000/CLK_KHZ_IN ;
logic [2:0] phase_cs;
logic phase_step,phase_updn;
logic phase_done;
// *********************************************************************************************
// This module generates the master reference clocks for the entire memory system.
// *********************************************************************************************
BrianHG_DDR3_PLL #(.FPGA_VENDOR (FPGA_VENDOR), .INTERFACE_SPEED (INTERFACE_SPEED), .DDR_TRICK_MTPS_CAP (DDR_TRICK_MTPS_CAP),
.CLK_KHZ_IN (CLK_KHZ_IN), .CLK_IN_MULT (CLK_IN_MULT), .CLK_IN_DIV (CLK_IN_DIV),
.DDR3_WDQ_PHASE (DDR3_WDQ_PHASE), .DDR3_RDQ_PHASE (DDR3_RDQ_PHASE)
) DUT_DDR3_PLL ( .RST_IN (RST_IN), .RST_OUT (RESET), .CLK_IN (CLK_IN), .DDR3_CK (DDR3_CLK),
.DDR3_CLK_WDQ (DDR3_CLK_WDQ), .DDR3_CLK_RDQ (DDR3_CLK_RDQ), .CMD_CLK (CMD_CLK), .PLL_LOCKED (PLL_LOCKED),
.phase_cs ( phase_cs ), .phase_step ( phase_step ), .phase_updn ( phase_updn ),
.phase_sclk ( CLK_IN ), .phase_done ( phase_done ) );
// ******************************************************************************************************
// This module receives the commands from the multi-port ram controller and sequences the DDR3 IO pins.
// ******************************************************************************************************
BrianHG_DDR3_PHY_SEQ #(.FPGA_VENDOR (FPGA_VENDOR), .FPGA_FAMILY (FPGA_FAMILY), .INTERFACE_SPEED (INTERFACE_SPEED),
.CLK_KHZ_IN (CLK_KHZ_IN), .CLK_IN_MULT (CLK_IN_MULT), .CLK_IN_DIV (CLK_IN_DIV),
.DDR3_CK_MHZ (DDR3_CK_MHZ), .DDR3_SPEED_GRADE (DDR3_SPEED_GRADE), .DDR3_SIZE_GB (DDR3_SIZE_GB),
.DDR3_WIDTH_DQ (DDR3_WIDTH_DQ), .DDR3_NUM_CHIPS (DDR3_NUM_CHIPS), .DDR3_NUM_CK (DDR3_NUM_CK),
.DDR3_WIDTH_ADDR (DDR3_WIDTH_ADDR), .DDR3_WIDTH_BANK (DDR3_WIDTH_BANK), .DDR3_WIDTH_CAS (DDR3_WIDTH_CAS),
.DDR3_WIDTH_DM (DDR3_WIDTH_DM), .DDR3_WIDTH_DQS (DDR3_WIDTH_DQS), .DDR3_ODT_RTT (DDR3_ODT_RTT),
.DDR3_RZQ (DDR3_RZQ), .DDR3_TEMP (DDR3_TEMP), .DDR3_WDQ_PHASE (DDR3_WDQ_PHASE),
.DDR3_RDQ_PHASE (DDR3_RDQ_PHASE), .DDR3_MAX_REF_QUEUE (DDR3_MAX_REF_QUEUE), .IDLE_TIME_uSx10 (IDLE_TIME_uSx10),
.POWR_UP_TIMER_uS (POWR_UP_TIMER_uS), .BANK_ROW_ORDER (BANK_ROW_ORDER),
.PORT_VECTOR_SIZE (PORT_VECTOR_SIZE), .PORT_ADDR_SIZE (PORT_ADDR_SIZE)
) DUT_PHY_SEQ ( // *** DDR3_PHY_SEQ Clocks & Reset ***
.RST_IN (RESET), .DDR_CLK (DDR3_CLK), .DDR_CLK_WDQ (DDR3_CLK_WDQ), .DDR_CLK_RDQ (DDR3_CLK_RDQ),
// *** DDR3 Ram Chip IO Pins ***
.DDR3_RESET_n (DDR3_RESET_n), .DDR3_CK_p (DDR3_CK_p), .DDR3_CKE (DDR3_CKE), .DDR3_CS_n (DDR3_CS_n),
.DDR3_RAS_n (DDR3_RAS_n), .DDR3_CAS_n (DDR3_CAS_n), .DDR3_WE_n (DDR3_WE_n), .DDR3_ODT (DDR3_ODT),
.DDR3_A (DDR3_A), .DDR3_BA (DDR3_BA), .DDR3_DM (DDR3_DM), .DDR3_DQ (DDR3_DQ),
.DDR3_DQS_p (DDR3_DQS_p), .DDR3_DQS_n (DDR3_DQS_n), .DDR3_CK_n (DDR3_CK_n),
// *** Command port input ***
.SEQ_CMD_CLK (CMD_CLK), .SEQ_CMD_ENA_t (SEQ_CMD_ENA_t), .SEQ_WRITE_ENA (SEQ_WRITE_ENA),
.SEQ_ADDR (SEQ_ADDR), .SEQ_WDATA (SEQ_WDATA), .SEQ_WMASK (SEQ_WMASK),
.SEQ_RDATA_VECT_IN (SEQ_RDATA_VECT_IN), .SEQ_refresh_hold (SEQ_refresh_hold),
// *** Command port results ***
.SEQ_BUSY_t (SEQ_BUSY_t), .SEQ_RDATA_RDY_t (SEQ_RDATA_RDY_t), .SEQ_RDATA (SEQ_RDATA),
.SEQ_RDATA_VECT_OUT (SEQ_RDATA_VECT_OUT), .SEQ_refresh_queue (SEQ_refresh_queue),
// *** Diagnostic flags ***
.SEQ_CAL_PASS (SEQ_CAL_PASS), .DDR3_READY (DDR3_READY) );
// ***********************************************************************************************
//************************************************************************************************************************************************************
//*** DDR3 Verilog model from Micron Required for this test-bench.
//************************************************************************************************************************************************************
`include "ddr3.v"
//************************************************************************************************************************************************************
//*** DDR3 Verilog model from Micron Required for this test-bench.
//*** The required DDR3 SDRAM Verilog Model V1.74 available at:
//*** [url]https://media-www.micron.com/-/media/client/global/documents/products/sim-model/dram/ddr3/ddr3-sdram-verilog-model.zip?rev=925a8a05204e4b5c9c1364302de60126[/url]
//*** From the 'DDR3 SDRAM Verilog Model.zip', only these 2 files are required in the main simulation test-bench source folder:
//*** ddr3.v
//*** 4096Mb_ddr3_parameters.vh
//************************************************************************************************************************************************************
// component instantiation
ddr3 sdramddr3_0 (
.rst_n ( DDR3_RESET_n ),
.ck ( DDR3_CK_p[0] ),
.ck_n ( DDR3_CK_n[0] ),
.cke ( DDR3_CKE ),
.cs_n ( DDR3_CS_n ),
.ras_n ( DDR3_RAS_n ),
.cas_n ( DDR3_CAS_n ),
.we_n ( DDR3_WE_n ),
.dm_tdqs ( DDR3_DM ),
.ba ( DDR3_BA ),
.addr ( DDR3_A ),
.dq ( DDR3_DQ ),
.dqs ( DDR3_DQS_p ),
.dqs_n ( DDR3_DQS_n ),
.tdqs_n ( ),
.odt ( DDR3_ODT )
);
//************************************************************************************************************************************************************
//************************************************************************************************************************************************************
//************************************************************************************************************************************************************
logic [7:0] WDT_COUNTER; // Wait for 15 clocks or inactivity before forcing a simulation stop.
logic WAIT_IDLE = 0; // When high, insert a idle wait before every command.
localparam int WDT_RESET_TIME = 255; // Set the WDT timeout clock cycles.
localparam int SYS_IDLE_TIME = WDT_RESET_TIME-64; // Consider system idle after 12 clocks of inactivity.
localparam real DDR3_CK_MHZ_REAL = CLK_KHZ_IN * CLK_IN_MULT / CLK_IN_DIV / 1000 ; // Generate the DDR3 CK clock frequency.
localparam real DDR3_CK_PERIOD = 1000 / DDR3_CK_MHZ_REAL ; // Generate the DDR3 CK period in nanoseconds.
initial begin
WDT_COUNTER = WDT_RESET_TIME ; // Set the initial inactivity timer to maximum so that the code later-on wont immediately stop the simulation.
SEQ_CMD_ENA_t = 0 ;
SEQ_WRITE_ENA = 0 ;
SEQ_ADDR = 0 ;
SEQ_WDATA = 0 ;
SEQ_WMASK = 0 ;
SEQ_RDATA_VECT_IN = 0 ;
SEQ_refresh_hold = 0 ;
phase_cs = 3'b000 ;
phase_step = 1'b0 ;
phase_updn = 1'b0 ;
RST_IN = 1'b1 ; // Reset input
CLK_IN = 1'b0 ;
#(50000);
RST_IN = 1'b0 ; // Release reset at 50ns.
while (!PLL_LOCKED) @(negedge CMD_CLK);
execute_ascii_file(TB_COMMAND_SCRIPT_FILE);
end
always #period CLK_IN = !CLK_IN; // create source clock oscillator
always @(posedge CLK_IN) WDT_COUNTER = (SEQ_BUSY_t!=SEQ_CMD_ENA_t) ? WDT_RESET_TIME : (WDT_COUNTER-1'b1) ; // Setup a simulation inactivity watchdog countdown timer.
always @(posedge CLK_IN) if (WDT_COUNTER==0) begin
Script_CMD = "*** WDT_STOP ***" ;
$stop; // Automatically stop the simulation if the inactivity timer reaches 0.
end
As you can see, I define a clock period and have my PLL, DDR3_PHY_SEQencer & Micron's ddr3.v wired together.
Then at initialize, I set the power-up defaults.
Then I wait for the PLL lock.
Then I execute my command script, (you may ignore this)
Then, at 'always #period CLK_IN = !CLK_IN; // create source clock oscillator' I am synthesizing the clock.
The next 2 lines, I am counting clock cycles and if there is no activity on the DDR3 sequencer command for enough clock cycles, I tell the simulator to $stop. At this point, the simulation waveform is viewable.
Don't worry about those 3 errors, I get the same 3 divide by 0 errors. It does not stop the simulation from working...
It appears that the initial startup works.
If you run the simulation for 1ps, then your waveform will be too short to see anything on the waveform.
Try running it for 1000ns, or 1us... Or even 10us...
Note that if you have a powerup timer set to the multi-ms range, then you need to run the simulation that long to get to that point.
thanks for reminding me to use "always #PERIOD clk = ~clk;"
It helps to solve the simulation forever running issue, but the simulation output waveform is empty (no data). Why ?
Besides, what do you exactly mean by "period figures should be in picoseconds, not nanoseconds." ?
I am already using : `timescale 1ns / 10ps // time-unit = 1 ns, precision = 10 ps
The timescale of 1ps/1ps is the specified value to use in Micron's ddr3.v, so, I wouldn't play with that.
I used the 1ps/1ps & the sim is accurate.
As for no data, step 1, go to your test_DDR3_controller on the 'sim' tab on the left.
In the objects window, all the wires which are there should show up.
Right Click on your 'clk' and 'resetn' and add-wave.
Restart & run the sim, and those 2 should show in your waveform.
I assume the 'no-data' may just be un-wired ports, or some changes you recently made has altered the base names of the ports. They may just need to be cleared from the waveform and re-placed the same way you just did it with the 'clk' and 'resetn' signals.
I have solved the 200us reset timing violation in previous post.
Now, I am having tIs violation inside
STATE_INIT_MRS_2 . Do you have any idea how to get around this particular timing violation ?
# test_ddr3_memory_controller.mem.main: at time 924036300.0 ps ERROR: tIS violation on CKE by 350.0 ps
# test_ddr3_memory_controller.mem.cmd_task: at time 924036300.0 ps ERROR: NOP or Deselect is required when CKE goes active.
# test_ddr3_memory_controller.mem.main: at time 924247500.0 ps ERROR: tIS violation on CS_N by 350.0 ps
# test_ddr3_memory_controller.mem.main: at time 924247500.0 ps ERROR: tIS violation on RAS_N by 350.0 ps
# test_ddr3_memory_controller.mem.main: at time 924247500.0 ps ERROR: tIS violation on CAS_N by 350.0 ps
# test_ddr3_memory_controller.mem.main: at time 924247500.0 ps ERROR: tIS violation on ADDR 0 by 350.0 ps
# test_ddr3_memory_controller.mem.main: at time 924247500.0 ps ERROR: tIS violation on ADDR 1 by 350.0 ps
# test_ddr3_memory_controller.mem.main: at time 924247500.0 ps ERROR: tIS violation on ADDR 2 by 350.0 ps
# test_ddr3_memory_controller.mem.main: at time 924247500.0 ps ERROR: tIS violation on ADDR 3 by 350.0 ps
# test_ddr3_memory_controller.mem.main: at time 924247500.0 ps ERROR: tIS violation on ADDR 4 by 350.0 ps
# test_ddr3_memory_controller.mem.main: at time 924247500.0 ps ERROR: tIS violation on ADDR 5 by 350.0 ps
# test_ddr3_memory_controller.mem.main: at time 924247500.0 ps ERROR: tIS violation on ADDR 6 by 350.0 ps
# test_ddr3_memory_controller.mem.main: at time 924247500.0 ps ERROR: tIS violation on ADDR 7 by 350.0 ps
# test_ddr3_memory_controller.mem.main: at time 924247500.0 ps ERROR: tIS violation on ADDR 8 by 350.0 ps
# test_ddr3_memory_controller.mem.main: at time 924247500.0 ps ERROR: tIS violation on ADDR 9 by 350.0 ps
# test_ddr3_memory_controller.mem.main: at time 924247500.0 ps ERROR: tIS violation on ADDR 10 by 350.0 ps
# test_ddr3_memory_controller.mem.main: at time 924247500.0 ps ERROR: tIS violation on ADDR 11 by 350.0 ps
# test_ddr3_memory_controller.mem.main: at time 924247500.0 ps ERROR: tIS violation on ADDR 12 by 350.0 ps
# test_ddr3_memory_controller.mem.main: at time 924247500.0 ps ERROR: tIS violation on ADDR 13 by 350.0 ps
# test_ddr3_memory_controller.mem.main: at time 924247500.0 ps ERROR: tIS violation on ADDR 14 by 350.0 ps
# test_ddr3_memory_controller.mem.main: at time 924247500.0 ps ERROR: tIS violation on ADDR 15 by 350.0 ps
Note: I have attached a zip file containing the Modelsim timing violation log file reported by Micron simulation model as well as the vcd waveform file exported out from Modelsim.
Did you search the Micron DDR3 datasheet to see what the tIS timing should be?
Did you zoom into your output waveform to see if the timing is met?
I got you to the point where the DDR3.v model seems to be working. It is now your job to make your DDR3 ram controller function without any violations.
Look at my initialize sequence screenshot on the previous forum page. It is zoomed in enough to show you what the waveform should look like with all the DDR3 pins in the middle except for CLKn. And if you compare it to the visual diagrams in the DDR3 datasheet, and look at the time scale in my screenshot, you will see a compliant match.
Do multiple searches in the data sheet. Look at table 45 in the data sheet, tIS is the setup time for a command, IE the time the command on the address[]/ba[]/ras/cas/cke.. must be set prior to the rising of the positive clock CK going into the DDR3 ram chip. (READ the next ~4 pages including the entire page on where table 45 is located. It tells you how your commands should look like to the DDR3 ram chip in relation to the CK & CK# clock inputs. It is all about the tIS and tIH, it's not just the first command, but everything you send to the DDR3.)
Now, go back to your simulation.
zoom in, way in so that you only see around 2-4 nanoseconds from left to right.
Then double click in the console on one of the tIS violation errors so that the waveform view will automatically re-center to that time position so you may inspect the error.
Look at your rising clock edge and when you send the commands, are those IOs set to their valid figures before your DDR3 positive CK pin goes from low to high by at least by the tIS picoseconds listed on table 45 the datasheet?
Now, take a look at my screenshot of my power-up sequence and look at when my DDR3_CK pin goes high. Look at my address[]/ba[]/ras/cas/cke... Are all those IOs properly setup and steady before my DDR3_CK pin transitions from low to high by the picosecond specification listed in table 45? Also, what about the tIH, the hold-time required after the clock transitions from low to high?
I've attached a closeup of my first MR2 so you can see the timing difference between my command & clock transition compared to yours. (Note, my clock in the sim is actually 500MHz, but this has no bearing on your tIS problem. Your timing should be far easier to achieve as you clock is slower...)
Please organize your sim so that your DDR3 IOs are organized the same as in my illustration labeled (A).
Then expand your address bus like seen in my illustration labeled (B).
Then select the 'Error' and zoom in with enough room to see a just a bit to the left and right as in my illustration labeled (C).
Then provide a proper screenshot of the waveform.
EXTRA: It may also visually help if your waveform grid preferences to matche your DDR3 clock cycle.
Yes, that too.
It is your code generating the Load Mode command right there...
Take a look at the command lines... It's a load mode BA=0 right there in front of your eyes.
It was generated by your ram controller...
Make an on-off parameter option to shrink your power-up reset time to 1us. Recompile and simulate in Modelsim without waiting for those 700us to simulate only takes a second to render your waveform results instead of ~45 seconds for every shot.
Only turn on the full 700us power-up timer after you get everything else right.
Micron's DDR3 model will allow you to get away with this with only 2 warnings right at the beginning of your sim.