defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
************************ altsyncram_component.init_file = "../osd_mem.mif", *************************************
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = NUM_WORDS,
altsyncram_component.numwords_b = NUM_WORDS,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "OLD_DATA",
altsyncram_component.read_during_write_mode_port_b = "OLD_DATA",
altsyncram_component.widthad_a = ADDR_SIZE,
altsyncram_component.widthad_b = ADDR_SIZE,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1",
altsyncram_component.init_file = "gpu_16K_RAM.mif";
Don't outputs from modules have to be wires? So cmd_mux_out should be a wire that is assigned to a reg somewhere else?
Have tried this, with cmd_tmp_out being a wire on the cmd_out output of the module, and with the cmd_mux_out <= cmd_tmp_out in the always block, but still getting a black screen.
Your .mif file is still wrong and it should be in the main file path.
here is what you have now:
altsyncram_component.init_file = "../osd_mem.mif",Code: [Select]defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
************************ altsyncram_component.init_file = "../osd_mem.mif", *************************************
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = NUM_WORDS,
altsyncram_component.numwords_b = NUM_WORDS,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "OLD_DATA",
altsyncram_component.read_during_write_mode_port_b = "OLD_DATA",
altsyncram_component.widthad_a = ADDR_SIZE,
altsyncram_component.widthad_b = ADDR_SIZE,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1",
altsyncram_component.init_file = "gpu_16K_RAM.mif";
also, make:
.write_ena_b(1'b1),
into a
.write_ena_b(1'b0),
Your not writing anything to ram....
The only difference I could find is this: (See red)
// this moves the data up one word at a time, dropping the top most 8 bits
addr_pipe[19:0] <= addr_mux_out;
addr_pipe[DEMUX_PIPE_TOP*20+19:1*20] <= addr_pipe[(DEMUX_PIPE_TOP-1)*20+19:0*20];
cmd_pipe[15:0] <= cmd_mux_out[15:0];
cmd_pipe[DEMUX_PIPE_TOP*16+15:1*16] <= cmd_pipe[(DEMUX_PIPE_TOP-1)*16+15:0*16];
Check your compiler reports and see how much 'ram' is being used...
Flow Status Successful - Tue Nov 12 15:16:18 2019
Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
Family Cyclone IV E
Device EP4CE6E22C8
Timing Models Final
Total logic elements 168 / 6,272 ( 3 % )
Total registers 127
Total pins 10 / 92 ( 11 % )
Total virtual pins 0
Total memory bits 8,224 / 276,480 ( 3 % )
Embedded Multiplier 9-bit elements 0 / 30 ( 0 % )
Total PLLs 1 / 2 ( 50 % )
Code: [Select]Flow Status Successful - Tue Nov 12 15:16:18 2019
Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
Family Cyclone IV E
Device EP4CE6E22C8
Timing Models Final
Total logic elements 168 / 6,272 ( 3 % )
Total registers 127
Total pins 10 / 92 ( 11 % )
Total virtual pins 0
Total memory bits 8,224 / 276,480 ( 3 % )
Embedded Multiplier 9-bit elements 0 / 30 ( 0 % )
Total PLLs 1 / 2 ( 50 % )
Still just a black screen...
module gpu_dual_port_ram_INTEL (
// inputs
input clk,
input [3:0] pc_ena_in,
input clk_b,
input wr_en_b,
input [19:0] addr_a,
input [19:0] addr_b,
input [7:0] data_in_b,
input [15:0] cmd_in,
// registered outputs
output reg [19:0] addr_out_a,
output reg [3:0] pc_ena_out,
output reg [15:0] cmd_out,
// direct outputs
output wire [7:0] data_out_a,
output wire [7:0] data_out_b
);
// define the maximum address bit
parameter ADDR_SIZE = 14;
// define the memory size (number of words) - this allows RAM sizes other than multiples of 2
// but defaults to power-of-two sizing based on ADDR_SIZE if not otherwise specified
parameter NUM_WORDS = 16384;
// define delay pipe registers
reg [19:0] rd_addr_pipe_a;
reg [15:0] cmd_pipe;
reg [3:0] pc_ena_pipe;
// ****************************************************************************************************************************
// Dual-port GPU RAM
//
// Port A - read only by GPU
// Port B - read/writeable by host system
// Data buses - 8 bits / 1 byte wide
// Address buses - ADDR_SIZE wide (14 bits default)
// Memory word size - NUM_WORDS (16384 bytes default)
// ****************************************************************************************************************************
altsyncram altsyncram_component (
.clock0 (clk),
.wren_a (1'b0),
.address_b (addr_b[13:0]),
.clock1 (clk_b),
.data_b (data_in_b),
.wren_b (wr_en_b),
.address_a (addr_a[13:0]),
.data_a (8'b00000000),
.q_a (data_out_a),
.q_b (data_out_b),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.init_file = "../gpu_16K_RAM.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16384,
altsyncram_component.numwords_b = 16384,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "OLD_DATA",
altsyncram_component.read_during_write_mode_port_b = "OLD_DATA",
altsyncram_component.widthad_a = 14,
altsyncram_component.widthad_b = 14,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
// ****************************************************************************************************************************
always @(posedge clk) begin
// **************************************************************************************************************************
// *** Create a serial pipe where the PIPE_DELAY parameter selects the pixel count delay for the xxx_in to the xxx_out ports
// **************************************************************************************************************************
rd_addr_pipe_a <= addr_a;
addr_out_a <= rd_addr_pipe_a;
cmd_pipe <= cmd_in;
cmd_out <= cmd_pipe;
pc_ena_pipe <= pc_ena_in;
pc_ena_out <= pc_ena_pipe;
// **************************************************************************************************************************
end
endmodule
Warning (14284): Synthesized away the following node(s):
Warning (14285): Synthesized away the following RAM node(s):
Warning (14320): Synthesized away node "vid_osd_generator:inst10|multiport_gpu_ram:gpu_RAM|gpu_dual_port_ram_INTEL:gpu_RAM|altsyncram:altsyncram_component|altsyncram_tnf2:auto_generated|ram_block1a8"
Warning (14320): Synthesized away node "vid_osd_generator:inst10|multiport_gpu_ram:gpu_RAM|gpu_dual_port_ram_INTEL:gpu_RAM|altsyncram:altsyncram_component|altsyncram_tnf2:auto_generated|ram_block1a9"
Warning (14320): Synthesized away node "vid_osd_generator:inst10|multiport_gpu_ram:gpu_RAM|gpu_dual_port_ram_INTEL:gpu_RAM|altsyncram:altsyncram_component|altsyncram_tnf2:auto_generated|ram_block1a10"
Warning (14320): Synthesized away node "vid_osd_generator:inst10|multiport_gpu_ram:gpu_RAM|gpu_dual_port_ram_INTEL:gpu_RAM|altsyncram:altsyncram_component|altsyncram_tnf2:auto_generated|ram_block1a11"
Warning (14320): Synthesized away node "vid_osd_generator:inst10|multiport_gpu_ram:gpu_RAM|gpu_dual_port_ram_INTEL:gpu_RAM|altsyncram:altsyncram_component|altsyncram_tnf2:auto_generated|ram_block1a12"
Warning (14320): Synthesized away node "vid_osd_generator:inst10|multiport_gpu_ram:gpu_RAM|gpu_dual_port_ram_INTEL:gpu_RAM|altsyncram:altsyncram_component|altsyncram_tnf2:auto_generated|ram_block1a13"
Warning (14320): Synthesized away node "vid_osd_generator:inst10|multiport_gpu_ram:gpu_RAM|gpu_dual_port_ram_INTEL:gpu_RAM|altsyncram:altsyncram_component|altsyncram_tnf2:auto_generated|ram_block1a14"
Warning (14320): Synthesized away node "vid_osd_generator:inst10|multiport_gpu_ram:gpu_RAM|gpu_dual_port_ram_INTEL:gpu_RAM|altsyncram:altsyncram_component|altsyncram_tnf2:auto_generated|ram_block1a15"
Not sure what's going on here in the compilation report:Code: [Select]Warning (14284): Synthesized away the following node(s):
Warning (14285): Synthesized away the following RAM node(s):
Warning (14320): Synthesized away node "vid_osd_generator:inst10|multiport_gpu_ram:gpu_RAM|gpu_dual_port_ram_INTEL:gpu_RAM|altsyncram:altsyncram_component|altsyncram_tnf2:auto_generated|ram_block1a8"
Warning (14320): Synthesized away node "vid_osd_generator:inst10|multiport_gpu_ram:gpu_RAM|gpu_dual_port_ram_INTEL:gpu_RAM|altsyncram:altsyncram_component|altsyncram_tnf2:auto_generated|ram_block1a9"
Warning (14320): Synthesized away node "vid_osd_generator:inst10|multiport_gpu_ram:gpu_RAM|gpu_dual_port_ram_INTEL:gpu_RAM|altsyncram:altsyncram_component|altsyncram_tnf2:auto_generated|ram_block1a10"
Warning (14320): Synthesized away node "vid_osd_generator:inst10|multiport_gpu_ram:gpu_RAM|gpu_dual_port_ram_INTEL:gpu_RAM|altsyncram:altsyncram_component|altsyncram_tnf2:auto_generated|ram_block1a11"
Warning (14320): Synthesized away node "vid_osd_generator:inst10|multiport_gpu_ram:gpu_RAM|gpu_dual_port_ram_INTEL:gpu_RAM|altsyncram:altsyncram_component|altsyncram_tnf2:auto_generated|ram_block1a12"
Warning (14320): Synthesized away node "vid_osd_generator:inst10|multiport_gpu_ram:gpu_RAM|gpu_dual_port_ram_INTEL:gpu_RAM|altsyncram:altsyncram_component|altsyncram_tnf2:auto_generated|ram_block1a13"
Warning (14320): Synthesized away node "vid_osd_generator:inst10|multiport_gpu_ram:gpu_RAM|gpu_dual_port_ram_INTEL:gpu_RAM|altsyncram:altsyncram_component|altsyncram_tnf2:auto_generated|ram_block1a14"
Warning (14320): Synthesized away node "vid_osd_generator:inst10|multiport_gpu_ram:gpu_RAM|gpu_dual_port_ram_INTEL:gpu_RAM|altsyncram:altsyncram_component|altsyncram_tnf2:auto_generated|ram_block1a15"
Quartus isn't saving the compilaton report as a file - there's probably a setting somewhere for it - although there is an export option in the r/click menu...
wire [7:0] sub_data_out_a; // ***NEW***
wire [7:0] data_out_a = sub_data_out_a[7:0]; // ***NEW***
wire [7:0] sub_data_out_b; // ***NEW***
wire [7:0] data_out_b = sub_data_out_b[7:0]; // ***NEW***
altsyncram altsyncram_component (
.clock0 (clk),
.wren_a (1'b1),
.address_b (addr_b[ADDR_SIZE - 1:0]),
.clock1 (clk_b),
.data_b (data_in_b),
.wren_b (wr_en_b),
.address_a (addr_a[ADDR_SIZE - 1:0]),
.data_a (8'b00000000),
.q_a (sub_data_out_a), // ***NEW******NEW******NEW******NEW***
.q_b (sub_data_out_b), // ***NEW******NEW******NEW******NEW***
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
Ok, try this one weird thing I used to have to do:
Inside "gpu_dual_port_ram_INTEL.v":Code: [Select]wire [7:0] sub_data_out_a; // ***NEW***
wire [7:0] data_out_a = sub_data_out_a[7:0]; // ***NEW***
wire [7:0] sub_data_out_b; // ***NEW***
wire [7:0] data_out_b = sub_data_out_b[7:0]; // ***NEW***
wire [7:0] data_out_a = sub_data_out_a[7:0]; // ***NEW***
wire [7:0] data_out_b = sub_data_out_b[7:0]; // ***NEW***
assign data_out_a = sub_data_out_a[7:0]; // ***NEW***
assign data_out_b = sub_data_out_b[7:0]; // ***NEW***
ALSO: you have not set the ".defparam" for the multiport_gpu_ram gpu_RAM() in the osd generator, though, the sub_modules should have ended up using their default values.
I'm downloading QuartusPrime 18.1 now. How big is you project in .zip?
wire [15:0] cmd_mux_out;
assign read_text_adr[19:10] = 1'h4;
....
assign read_font_adr[19:10] = 1'h2;
assign read_text_adr[19:10] = 10'h4; // my mistake, I has 1bit instead of 10bits
......
assign read_font_adr[19:10] = 10'h2; // my mistake, I has 1bit instead of 10bits
parameter PIXEL_PIPE = 3; // This externally set parameter defines the number of 25MHz pixels it takes to receive a new pixel from a presented address
localparam CLK_CYCLES_MUX = 1; // adjust this parameter to the number of 'clk' cycles it takes to select 1 of 5 muxed outputs
localparam CLK_CYCLES_RAM = 2; // adjust this figure to the number of clock cycles the DP_ram takes to retrieve valid data from the read address in
localparam CLK_CYCLES_PIX = 5; // adjust this figure to the number of 125MHz clocks there are for each pixel, IE number of muxed inputs for each pixel
// This parameter begins with the wanted top number of 125Mhz pixel clock headroom for the pixel pipe, then subtracts the additional 125MHz clocks used by the _MUX and _RAM cycles used to arrive at the first pixel out, DEMUX_PIPE_TOP position.
localparam DEMUX_PIPE_TOP = (( (PIXEL_PIPE - 1) * CLK_CYCLES_PIX ) - 1) - CLK_CYCLES_MUX - CLK_CYCLES_RAM;
localparam MUX_0_POS = DEMUX_PIPE_TOP - 0; // pixel offset positions in their respective synchronisation
localparam MUX_1_POS = DEMUX_PIPE_TOP - 1; // pipelines (where the pixels will be found in the pipeline
localparam MUX_2_POS = DEMUX_PIPE_TOP - 2; // when pc_ena[3:0]==0).
localparam MUX_3_POS = DEMUX_PIPE_TOP - 3; //
localparam MUX_4_POS = DEMUX_PIPE_TOP - 4; //
// Now that we know the DEMUX_PIPE_TOP, we can assign the top size of the 3 pipe regs
reg [DEMUX_PIPE_TOP*8+7:0] data_pipe;
reg [DEMUX_PIPE_TOP*20+19:0] addr_pipe;
reg [DEMUX_PIPE_TOP*16+15:0] cmd_pipe;
always @(posedge clk) begin
// We also need to limit the pipe in the 3 ' <= '
data_pipe[7:0] <= data_mux_out[7:0]; // fill the first 8-bit word in the register pipe with data from RAM
data_pipe[DEMUX_PIPE_TOP*8+7:1*8] <= data_pipe[ (DEMUX_PIPE_TOP-1) *8+7:0*8]; // shift over the next 9 words in this 10 word, 8-bit wide pipe
// this moves the data up one word at a time, dropping the top most 8 bits
addr_pipe[19:0] <= addr_mux_out;
addr_pipe[DEMUX_PIPE_TOP*20+19:1*20] <= addr_pipe[ (DEMUX_PIPE_TOP-1) *20+19:0*20];
cmd_pipe[15:0] <= cmd_mux_out[15:0];
cmd_pipe[DEMUX_PIPE_TOP*16+15:1*16] <= cmd_pipe[ (DEMUX_PIPE_TOP-1) *16+15:0*16];
Found it!
...I've attached the latest verilog files for you to use. Also don't forget to update our top block diagram file with the OSD generator's new pipeline delay as it may still be 4. It might be best to re-generate symbol files and clear & re-insert the OSD generator in you block diagram to clear out any old junk.
There is only the matter of patching your 'mux' in the multiport ram module, however, you should now be getting a picture. If so, I'll explain the patch and everything should work.
// ****************************************************************************************************************************
// Dual-port GPU RAM
//
// Port A - read only by GPU
// Port B - read/writeable by host system
// Data buses - 8 bits / 1 byte wide
// Address buses - ADDR_SIZE wide (14 bits default)
// Memory word size - NUM_WORDS (16384 bytes default)
// ****************************************************************************************************************************
altsyncram altsyncram_component (
.clock0 (clk),
.wren_a (1'b1), ************************F--K******************
.address_b (addr_b[ADDR_SIZE - 1:0]),
.clock1 (clk_b),
.data_b (data_in_b),
.wren_b (wr_en_b),
.address_a (addr_a[ADDR_SIZE - 1:0]),
.data_a (8'b00000000),
.q_a (data_out_a),
.q_b (data_out_b),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
.wren_a (1'b1), **********F--K***********// perform 5:1 mux for all inputs to the dual-port RAM
case (pc_ena_in[2:0])
3'b000 : begin //******** Excellent, this is state 0 and you made the case 3'b000 which equals 0.
addr_in_mux <= addr_in_0;
cmd_mux_in <= cmd_in_0;
end
3'b001 : begin //******** Excellent, this is state 1 and you made the case 3'b001 which equals 1.
addr_in_mux <= addr_in_1;
cmd_mux_in <= cmd_in_1;
end
3'b011 : begin //******** Hun? What? This is state 2 and you made the case 3'b011 which equals 3?
addr_in_mux <= addr_in_2;
cmd_mux_in <= cmd_in_2;
end
3'b100 : begin //******** Hun? What? This is state 3 and you made the case 3'b100 which equals 4?
addr_in_mux <= addr_in_3;
cmd_mux_in <= cmd_in_3;
end
3'b101 : begin //******** Hun? What? This is state 4 and you made the case 3'b101 which equals 5?
addr_in_mux <= addr_in_4;
cmd_mux_in <= cmd_in_4;
end
endcase
case (pc_ena_in[2:0])
3'b000 : begin
addr_in_mux <= addr_in_0; // Send the first, #0 addr & cmd to the memory module.
cmd_mux_in <= cmd_in_0;
addr_lat_1 <= addr_in_1; // latch all addr_in_# in parallel
addr_lat_2 <= addr_in_2;
addr_lat_3 <= addr_in_3;
addr_lat_4 <= addr_in_4;
cmd_lat_1 <= cmd_in_1; // latch all cmd_in_# in parallel
cmd_lat_2 <= cmd_in_2;
cmd_lat_3 <= cmd_in_3;
cmd_lat_4 <= cmd_in_4;
end
3'b001 : begin
addr_in_mux <= addr_lat_1; // Send the latched, #1 addr & cmd to the memory module.
cmd_mux_in <= cmd_lat_1;
end
3'b010 : begin
addr_in_mux <= addr_lat_2; // Send the latched, #2 addr & cmd to the memory module.
cmd_mux_in <= cmd_lat_2;
end
3'b011 : begin
addr_in_mux <= addr_lat_3; // Send the latched, #3 addr & cmd to the memory module.
cmd_mux_in <= cmd_lat_3;
end
3'b100 : begin
addr_in_mux <= addr_lat_4; // Send the latched, #4 addr & cmd to the memory module.
cmd_mux_in <= cmd_lat_4;
end
endcase
https://www.intel.com/content/www/us/en/programmable/downloads/software/quartus-ii-we/91sp2.html
@nockieboy, I'M GONNA MURDER YOU!!!!!!!
Let's begin...
...You made the Write Enable for the read address forced on!!!!!!!!
Every address we sent to be read was instead written clear to all 0's.
It gets worse, in you mux algorithm in the 'multiport_gpu_ram.v' module, you did this:Quote// perform 5:1 mux for all inputs to the dual-port RAM
case (pc_ena_in[2:0])
3'b000 : begin //******** Excellent, this is state 0 and you made the case 3'b000 which equals 0.
addr_in_mux <= addr_in_0;
cmd_mux_in <= cmd_in_0;
end
3'b001 : begin //******** Excellent, this is state 1 and you made the case 3'b001 which equals 1.
addr_in_mux <= addr_in_1;
cmd_mux_in <= cmd_in_1;
end
3'b011 : begin //******** Hun? What? This is state 2 and you made the case 3'b011 which equals 3?
addr_in_mux <= addr_in_2;
cmd_mux_in <= cmd_in_2;
end
3'b100 : begin //******** Hun? What? This is state 3 and you made the case 3'b100 which equals 4?
addr_in_mux <= addr_in_3;
cmd_mux_in <= cmd_in_3;
end
3'b101 : begin //******** Hun? What? This is state 4 and you made the case 3'b101 which equals 5?
addr_in_mux <= addr_in_4;
cmd_mux_in <= cmd_in_4;
end
endcase
defparam gpu_RAM.ADDR_SIZE = 14, // pass ADDR_SIZE into the gpu_RAM instance
gpu_RAM.PIXEL_PIPE = 2; // set the length of the pixel pipe to offset multi-read port sequencing
if (pc_ena[3:2] == 0) // once per pixel
Ookay... switched to the clean project now, added a PLL and just had to change a timing error in the sync generator on line 67:Code: [Select]if (pc_ena[3:2] == 0) // once per pixel
... was too slow for the monitor - changed it to pc_ena[2:0] and I'm getting this picture now:
(Attachment Link)
Ookay... switched to the clean project now, added a PLL and just had to change a timing error in the sync generator on line 67:Code: [Select]if (pc_ena[3:2] == 0) // once per pixel
... was too slow for the monitor - changed it to pc_ena[2:0] and I'm getting this picture now:
(Attachment Link)
assign font_pos[12:6] = letter[6:0] ; // Select the upper font address with the 7 bit letter, note the atari font has only 128 characters.
assign font_pos[2:0] = dly3_disp_y[3:1] ; // select the font x coordinate with a 2 pixel clock DELAYED disp_x address. [3:1] is used so that every 2 x lines are repeats
assign font_pos[5:3] = dly3_disp_y[3:1] ; // select the font y coordinate with a 2 pixel clock DELAYED disp_y address. [3:1] is used so that every 2 y lines are repeats
It should be this way, and you had it this way since you were able to display the red text:assign font_pos[9:3] = letter[6:0] ; // Select the upper font address with the 7 bit letter, note the atari font has only 128 characters.
assign font_pos[2:0] = dly3_disp_y[3:1] ; // select the font x coordinate with a 2 pixel clock DELAYED disp_x address. [3:1] is used so that every 2 x lines are repeats
https://www.intel.com/content/www/us/en/programmable/downloads/software/quartus-ii-we/91sp2.html
Your going to need it for engineering the address generator.