Ok, the first 7E means for reading that byte, you need a 'WAIT' state for my DDR3 to retrieve the 16 byte block of ram while the other bytes are correct since they are cached & read as fast as core FPGA memory, so they appear fine until you enter a new block of ram.
Ok, could you try adding the dummy wait-state during any and all Z80 read GPU ram.
If done, this might fix the $7E read byte errors.
Ready
DUMP &C000
+0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F
C000 7E B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C010 7E 10 B0 10 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C020 7E B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C030 7E B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C040 7E B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C050 7E B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C060 7E B0 0F B0 12 B0 00 50 02 7F 01 DF 00 00 00 00 .......P........
C070 7E 01 0F B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C080 7E B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C090 7E B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C0A0 7E B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C0B0 7E B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C0C0 7E B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C0D0 7E B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C0E0 7E B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C0F0 7E B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
OUT 249,1 <---- set minimum WAIT insertion time
Ready
DUMP &C000
+0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F
C000 00 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C010 B0 10 B0 10 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C020 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C030 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C040 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C050 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C060 08 B0 0F B0 12 B0 00 50 02 7F 01 DF 00 00 00 00 .......P........
C070 B0 01 0F B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C080 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C090 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C0A0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C0B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C0C0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C0D0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C0E0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
C0F0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 ................
Could you setup Signaltap to capture a Z80 read cycle showing the added CMD_R/W bus, including the 'busy' signals.
Could you also send me a .bin of the last default power-up .mif.
Get the rs232 debugger working.
I will add a patch where the DDR3 writes will be copied to the 'data_mux_geo's .wr_ena_b, .address_b & .data_in_b so it will affect the core GPU ram.
@Nockieboy, are you getting a really dim image on the DECA board?
IE, do you need to boost your monitor's contrast really high?
@Nockieboy, are you getting a really dim image on the DECA board?
IE, do you need to boost your monitor's contrast really high?
Whoah. How did you know that? I've had my TV's brightness at 60 and contrast at 70 all this time since using the DECA's HDMI output. Normal values of 50/50 give a very dim screen.
Take a look at C06C and C000, why are those 2 = to 0x00?
Are you sure you haven't poked all 0s to the ram?
; X & Y scale (set to 0 for 1:1 scaling)
LD HL,0000H
LD (GPU_RAM+6CH),HL
; X & Y sub-pixel position (set to 0,0)
LD (GPU_RAM+6EH),HL
Also, the Z80 bridge might not know for how long to hold the output enable if the DDR3 controller reads back data immediately.
Is the rd_DAT_ready tied to my CMD_read_ready?
Where are the CMD_R/W_busy signals?
Okay, no WAITs, added what I could to the node list with the proviso mentioned in my previous post about Quartus seeming to optimise out certain signals.
This below trace is the result of reading C000 (0x0000):
Z80_CLKr <= !Z80_CLK ; // Register delay the Z80_CLK input.
Where are the output enable and the 245 dir controls?
My guess the transition from 81h to 00h at time 22 is happening too late.
Take a look at what happens when you read 2 adjacent GPU ram bytes. Lets see how fast the second byte (which would be in my DDR3 controller's cache unless you read outside the 16 byte read cache) returns the data.
Here you go, a bunch of little patches.
Everything seems to work OK, other than I cannot test the Z80 interface.
Note that you will need to move the RS232 debugger's RXD/TXD pins. They are located on lines 561-563 in file 'GPU_DECA_DDR3_top.sv'.
Also, to disable my forced video ON even without a Z80 connected, goto line 555 and enter ( 1'b0 ) for that input.
I have not included the inverted Z80 clock test with these files.
Your picture brightness should now be correct.
You might need to re-enter your latest signal-tap nets.
Lest's get the Z80 working fine with the DDR3. Once done, we will move the geometry unit over to the DDR3, then, we will need to make the new MAGGIE & OSD / PALETTE system which will then run a display right from the DDR3 releasing you from your tiny 128k screen memory limit.
Well, the debugger should be reading and writing memory properly.
So, where are those '0B' errors coming from. They must be from Z80 writes. They cannot be from blits as those do not yet access the DDR3, they go exclusively to the FPGA block ram.
Well, the debugger should be reading and writing memory properly.
So, where are those '0B' errors coming from. They must be from Z80 writes. They cannot be from blits as those do not yet access the DDR3, they go exclusively to the FPGA block ram.
But nothing has changed on the Z80 side. The pre-DDR3 project worked perfectly, with no errors in reads or writes to GPU RAM.
Try editing/clearing the DDR3 in the debugger. Read back with the Z80 hex display. Re-check after a Z80 write and block write fill.
I need you to test the design. If it runs and Signaltap works, let me know so I can add the smart 'wait' routine.
dump &C000
+0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F
C000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C010 00 10 00 10 00 00 00 00 00 00 00 00 00 00 00 00 ................
C020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C060 08 00 0F 00 12 00 00 50 02 7F 01 DF 00 00 00 00 .......P........
C070 00 01 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C080 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C090 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C0A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C0B0 7E 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C0C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C0D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C0E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C0F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
Ready
DUMP &C000
+0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F
C000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C010 00 10 00 10 00 00 00 00 00 00 00 00 00 00 00 00 ................
C020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C060 08 00 0F 00 12 00 00 50 02 7F 01 DF 00 00 00 00 .......P........
C070 00 01 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C080 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C090 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C0A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C0B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C0C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C0D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C0E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C0F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
Ready