// Z80 bus timing settings.
.READ_PORT_CLK_POS ( 2 ), // Number of Z80_CLK cycles before the bus interface responds to a Read Port command.
.WRITE_PORT_CLK_POS ( 2 ), // Number of Z80_CLK cycles before the bus interface samples the Write Port command's data.
// 0 to 3, Number of CMD_CLK cycles to wait for DDR3 read before asserting the WAIT during a Read Memory cycle.
// Use 0 for an instant guaranteed 'WAIT' every read. (Safest for Read Instruction Opcode cycle.)
// Use 3 for compatibility with waiting for a BrianHG_DDR3 read cache hit before asserting the 'WAIT'.
.Z80_DELAY_WAIT_RI ( 0 ), // 0 to 4, Number of CMD_CLK cycles to wait for DDR3 read_ready before asserting the WAIT during a Read Instruction Opcode cycle.
.Z80_DELAY_WAIT_RM ( 3 ), // 0 to 4, Number of CMD_CLK cycles to wait for DDR3 read_ready before asserting the WAIT during a Read Memory cycle.
.Z80_WAIT_QUICK_OFF ( 1 ), // 0 (Default) = WAIT is turned off only during a low Z80_CLK. 1 = WAIT is turned off as soon as a read_ready is received.
// Read IO port addresses range.
.READ_PORT_BEGIN ( 240 ), // Sets the beginning port number which can be read.
.READ_PORT_END ( 249 ), // Sets the ending port number which can be read.
// ***********************************
// *** Z80 IO Read and Write ports ***
// ***********************************
output logic [255:0] WRITE_PORT_STROBE = 0 , // The bit [port_number] in this 256 bit bus will pulse when the Z80 writes to that port number.
output logic [7:0] WRITE_PORT_DATA [0:255] , // The array [port_number] will hold the last written data to that port number.
output logic [255:0] READ_PORT_STROBE = 0 , // The bit [port_number] in this 256 bit bus will pulse when the Z80 reads from that port number.
input wire [7:0] READ_PORT_DATA [0:255] , // The array [port_number] will be sent to the Z80 during a port read so long as the read port
// number is within parameter READ_PORT_BEGIN and READ_PORT_END.
Also, please provide the latched Z80_addr_r input instead of the mem-range. Something is fishy about the not in cache read req.
And I want to see a port read and port write. We will save the read-op-code for when the 'wait' is functioning.
*** What does the read DDR3 data look like on the Z80 display hex. Does it read correct data?
DUMP &C000
+0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F
C000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C010 00 10 00 10 00 00 00 00 00 00 00 00 00 00 00 00 ................
C020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C060 08 00 0F 00 12 00 00 50 02 7F 01 DF 00 00 00 00 .......P........
C070 00 01 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C080 7E 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C090 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C0A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C0B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C0C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C0D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C0E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C0F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
Ok, here you go, the hopefully final Z80 interface with 'WAIT' processing.
Ok, before I make final changes, please go through a flurry of tests.
Signaltap & Z80 read/write...
Looking at the CMD_read_ready[1], the length of those extended wait TW cycles are absurd.
Are you still using that junk transistor with the 200ns turn off?
What about the 'LDIR' clear screen trick?
If you cant get all the test signals, maybe we need to find their root source to tap.
Like, I really want to see the 'Z80_WAIT' output in the signaltap. It is kinda the important thing.
Here is another test.
It should stop flooding the DDR3 read requests after a read_ready has been received. (It's my multiport's cache system which prevents this trick from making my DDR3 controller PHY from going on a non-stop reading rampage.)
And one-shot the DDR3 writes.
Ok, here is V1.10 of the Z80 bus testbench and bus interface. Test it to see if it works and also fixes the read cache as last read cache you showed me here https://www.eevblog.com/forum/fpga/fpga-vga-controller-for-8-bit-computer/msg3737161/#msg3737161 didn't work, it sent the 'wait' anyways when it didn't need to.
By the way, there is no such thing as a write cache hit. Writes are always a cache hit. It's a question of if you can completely fill the write cache. To do this, the Z80 will need to be clocked at 4.8GHz if it were doing nothing but writing data in a straight line. But since it needs to read op-code to do the writing, make that >9GHz Z80.
I need to know if you can test reading opcode from GPU ram. It is important as it is worth running read opcodes through a second DDR3 read channel so they have their own separate 16 instruction cache compared to the read and write memory instructions. This might effect the either the maximum MAGGIE layers or GEO performance if you store OP-code in the DDR3. It's just a consideration.
I need to know if you can test reading opcode from GPU ram. It is important as it is worth running read opcodes through a second DDR3 read channel so they have their own separate 16 instruction cache compared to the read and write memory instructions. This might effect the either the maximum MAGGIE layers or GEO performance if you store OP-code in the DDR3. It's just a consideration.
Yes, no problem. I can write a little program and load it into page 1 of GPU RAM and execute it no problems. Although I can't really see any particular use for it - there's plenty of RAM available elsewhere.
DUMP &C100
+0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F
C100 3E 55 01 20 00 21 FF C0 77 2B 10 FC C9 00 00 00 >U. .!..w+......
C110 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C120 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C130 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C140 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C150 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C160 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C170 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C180 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C190 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C1A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C1B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C1C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C1D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C1E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C1F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
Ready
DASM &C100,&C
DISASSEMBLING C100h to C10Bh:
C100 3E 4E LD A,$55
C102 06 20 LD B,$20
C104 21 45 00 LD HL,C1FFH
C107 77 LD (HL),A
C108 2B DEC HL
C109 10 20 DJNZ C107H
C10B C9 RET
----------------
DUMP &C100
+0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F
C100 3E 55 06 20 21 FF C1 77 2B 10 FC C9 00 00 00 00 >U. !..w+.......
C110 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C120 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C130 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C140 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C150 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C160 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C170 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C180 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C190 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C1A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C1B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C1C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C1D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
C1E0 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 UUUUUUUUUUUUUUUU
C1F0 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 UUUUUUUUUUUUUUUU
.Z80_DELAY_WAIT_RI ( 2 ), // 0 to 7, Number of CMD_CLK cycles to wait for DDR3 read_ready before asserting the WAIT during a Read Instruction Opcode cycle.
And capture the second read opcode as this one should now be read from cache without any 'WAIT' inserted as my DDR3 will now return the data quick enough to not need to.