Plot those points on the same graph, and draw some lines through them for each of the 4 cases (2 lines, infinite/finite bandwidth).
i believe thats not what i was against to... i only asked to those of who that know what they are talking about. i initially lumped it as "definite wisdom" or "definite limited wisdom" to be more accurate? (check 2nd line my signature
) btw for the sake of it... let me check for those who know what they are talking the allknowing... here is from the ad9850 datasheet page 8
fOUT = (? Phase × CLKIN)/2^32
? Phase is the value of the 32-bit tuning word.
CLKIN=125MHz, calculating for the required 164KHz output, the tuning word will be 5634997 (the value is confirmed in the sim
http://www.analog.com/designtools/en/simdds/dtDDSMain.aspx), i just run a homemade simulator to simulate accumulator increment and overflow... for each 125MHz clock, hence for each accumulator adding its value... (attached file, i only did 380 iteration or clk since my ide report overflow error no thanks to my 32bit machine) 14bits MSB just as stated in datasheet are separated by "-". here summary the first 5 iteration
00000000000000 - 000000000000000000
00000000010101 - 011111101110110101
00000000101010 - 111111011101101010
00000001000000 - 011111001100011111
00000001010101 - 111110111011010100
but from the the math it will need 2^32 / 5634997 = 762 iterations before accumulator wrapped around back to zero, so theoritically... ideally.... the DDS should be able to output 762 of distinct and different lookup table values, clocked, jumping up and down at 125MHz rate, visible on the scope unfiltered, right? but in practice.... it is not so.... here recap again...
8 values, clocked or changing value at 1MHz point whatever, WTF?. the all knowing said there's no prescale going on. so let me conclude with what i meant by "definite wisdom" is, encapsulated in the black box of...
The AD9850 uses an innovative and proprietary
algorithm that mathematically converts the 14-bit truncated
value of the phase accumulator to the appropriate COS value.
This unique algorithm uses a much reduced ROM look-up table
and DSP techniques to perform this function, which contributes
to the small size and low power dissipation of the AD9850.
ad9850 datasheet page 8...
but still... it really doesnt make any sense... 762 iterations but only 8 meaningfull values output
one may argue that the picture posted by hamster is from different dds, but its more robust dss compared to 9850, still output alot less than whats ideal...
8 values, clocked or changing value at 1MHz point whatever, WTF?.
We've already established that this chip is not running at 125 MHz. Do the math again for 1 MHz. Hint: I don't think they're actually the same eight values, I think they're just close...
Another hint: If you divide the
actual clock (1.315789 MHz) by the 164 kHz frequency, you get 8.02 ...
the all knowing said there's no prescale going on. so let me conclude with what i meant by "definite wisdom" is, encapsulated in the black box of...
The AD9850 uses an innovative and proprietary
algorithm that mathematically converts the 14-bit truncated
value of the phase accumulator to the appropriate COS value.
This unique algorithm uses a much reduced ROM look-up table
and DSP techniques to perform this function, which contributes
to the small size and low power dissipation of the AD9850.
ad9850 datasheet page 8...
That "black box" doesn't affect the signal, if it's doing what I think it's doing. It just takes advantage of the fact that a sinusoid is symmetric multiple ways to reduce duplication and make the lookup table smaller - it'll reconstruct the
full sine wave using the "DSP techniques" they mention.
We've already established that this chip is not running at 125 MHz. Do the math again for 1 MHz.
no, in your respond, you directed to reply #61, reply #61 (basic dds) specifically said the chip is always runs at 125MHz, acummulator got added every 125MHz...
We've already established that this chip is not running at 125 MHz. Do the math again for 1 MHz.
no, in your respond, you directed to reply #61, reply #61 (basic dds) specifically said the chip is always runs at 125MHz, acummulator got added every 125MHz...
I was pointing you to the thought processes, not the numbers. I figured you were smart enough to notice the discrepancy and adjust for the different clock frequency.
We've already established that this chip is not running at 125 MHz. Do the math again for 1 MHz.
no, in your respond, you directed to reply #61, reply #61 (basic dds) specifically said the chip is always runs at 125MHz, acummulator got added every 125MHz...
I was pointing you to the thought processes, not the numbers. I figured you were smart enough to notice the discrepancy and adjust for the different clock frequency.
It's not going to change the clock frequency, Mecha. I feel like you have no idea what you're talking about.
thats only the basic "thought process". sorry if i misinterpret, but i really dont get you. i was "assuming" since its a blackbox, there's no mentioning how to calc at 1MHz, output sample frequency? whats that? its a black box i simply assuming its a "prescaled frequency" (that i believed you denied) from the base xtal. but its not there in the datasheet or elementary description. even if i do the math at 1MHz, i suspect it will still doesnt make any sense, 8 values at 164KHz? with 125MHz base freq, 16 bits everything? thats nonsensical in any imaginable numbers.
one may argue that the picture posted by hamster is from different dds, but its more robust dss compared to 9850, still output alot less than whats ideal...
Look, you still don't get it. Just because the
unfiltered output looks messed up, this doesn't mean that the
filtered output will look bad. "Ideal" output is the output that contains all required information to reconstruct the intended sine signal, using the reconstruction filter. In that sense, the 30MHz output of this AD9850 *is ideal*. You just have to follow the datasheet and add proper filtering, after which you will get a "perfect" sine. You can play around with that AD9850 tool on the AD website: set it to 30MHz, don't use a filter at first, and look at the crappy output. Then, click "config filter", set it to a 5th order filter of 42MHz, enable the filter, and watch the output again. Now it's a sine! That's what the filter will do for you. Just because the input to the filter contains frequencies ("images") other than the intended frequency (which makes it look staircased), the filter will remove those images, and what remains is the sine.
Now try setting the filter to 75MHz. Because the first "image" is at 95MHz (125MHz - 30MHz), and because the filter is not that steep, you will see a less than perfect sine. Now it happens that some of these cheap modules apparently were fitted with this wrong 75MHz filter (see
http://www.pongrance.com/DDS-9850.html). This explains the less than ideal output at 30MHz. From the very beginning of this thread it was mentioned that the filtering was probably not done well, and people started saying that even with good filtering, this AD9850 cannot produce a good output. This is simply not true.
So again, all this talk about "2 bits output", "4 bits output", "not going over all 1024 values", etc. etc. is not relevant. What's relevant is that
enough information is output to reconstruct the intended sine wave after filtering.
The device will add the frequency tuning word to the phase accumulator at a rate of the clock frequency, and then the phase accumulator goes to the lookup table. That's the basic DDS architecture.
With all values normalized to 1, fc = 1.3 MHz, f = 164 kHz.
f/fc = 0.126154 - this is the frequency tuning word.
Now add this over and over again, at a rate of 1.3 MHz / 769ns:
0.126154, 769ns
0.252308, 1.538462µs
0.378462, 2.307692µs
0.504615, 3.076923µs
0.630769, 3.846154µs
0.756923, 4.615385µs
0.883077, 5.384615µs
0.009231, 6.153846µs (overflow)
0.135386, 6.923077µs
0.261540, 7.692308µs
0.387694, 8.461538µs
0.513848, 9.230769µs
0.640002, 10µs
0.766156, 10.76923µs
0.892310, 11.53846µs
0.018464, 12.30769µs (overflow)
The frequency is approximately 1/6.153846µs or 162.5 kHz. The next time around it'll be a slight bit different because the overflow didn't occur at exactly an integer step, and the average frequency will work out to 164 kHz (write a script to run this for a large number of periods and calculate the frequency at the end, if you like).
No change in clock, no change in DAC resolution. There are eight steps per period, and you'll notice that the values look similar between the two periods I did, but they're not the same.
Edit: By the way, things start to get "interesting" when the set frequency is a nice integer ratio of the clock. Try it, you will lose a bit of effective resolution. There's a reason ADI's DDS sim gives a nice ugly warning if you set it up that way. But that's nothing to do with the DDS chip, that's math. Even this very basic accumulation will exhibit it.
Look, you still don't get it.
no it is you that dont get it. in fact it is your post that started it that i need to rectify.... and i and you was not talking anything yet about filtering. analog filtering is entirely a different story...
And this whole thing about 4 bits of DAC resolution still makes no sense. The part has a 10 bits DAC. It's not "2 steps, high and low", but 2^10 (1024) possible values
just as other said, can you distinguish a signal 0,1,0,1 and 0,1023,0,1023? no! at most maybe only the larger amplitude if the dds spit out 0,1024,0,1024. but still it is effectively only 1 bit output hi and lo, digitally speaking.
8 values...it makes sense (somewhat) if the accumulator value is truncated at the top end and sent to the DAC...eg. only the top 3 bits of the DAC are getting changed. But that doesn't seem to be the case in your particular case, so I don't know WTF...
My original point still stands...you aren't going to get a GOOD DDS Sig Gen for $12 off of chinabay.
Don't know if doing a quicky video on it is gonna do any good. I loaned out my Tek2465. All I've got here at the shop that's worth anything is a 2246. 100Mhz bandwidth may or may not be able to show some of the higher frequency content.
Mecha, read my comment above about what happens when the frequency set is an integer ratio of the clock frequency. Then some of the things you're spewing start to become valid, kinda-sorta-maybe. They don't have to, though, you just avoid that case in practice...
You'd do well to spend more time asking questions than making statements until you've figured this stuff out.
Skimask, stop with this "chinabay" bullshit. DDS is DDS. They all work more or less the same, with different amounts of filtering and different amounts of sample rate overhead.
At a few special frequency setting only some of the tabulated sin values are used. However this is not a disadvantage - after filtering it still results in a clean sine signal. Even if you don't use all possible steps of the DAC, the sine is not getting worse. The important part is how well the required steps are met. Depending on the DAC one may hit a sweep or weak spot of the DAC - thus you likely get the best (especially Phase noise) and worst values at these special frequencies. So spurious signals and noise will be somewhere is the -50 to -60 dB range, not much different from other frequencies.
With a well made filter these DDS chips are really quite powerful - so it's a pity that some of the Chinese Moduls seem to use poor filters. The question is a little why this setup seems to have an upper limit at about 1 MHz. This way of the expected behavior and can't be explained with simple tolerances. Tuning the LC filter so low even starts to get more difficult.
fc = 1.3 MHz
It's not going to change the clock frequency, Mecha. I feel like you have no idea what you're talking about.
you stated the clock wont change, i was talking about xtal freq of 125MHz got prescaled or something, and you denied it... now you talking about fc = 1.3MHz, i think you are in agreement with me, its just that you have no idea what i was talking about.
Skimask, stop with this "chinabay" bullshit. DDS is DDS. They all work more or less the same, with different amounts of filtering and different amounts of sample rate overhead.
Yes, DDS is DDS. I'm there. Better, worser, etc. This whole thing started with the notion that this particular DDS module can dump out a decent 30Mhz.
(I'm just here to start shit...
)
fc = 1.3 MHz
It's not going to change the clock frequency, Mecha. I feel like you have no idea what you're talking about.
you stated the clock wont change, i was talking about xtal freq of 125MHz got prescaled or something, and you denied it... now you talking about fc = 1.3MHz, i think you are in agreement with me, its just that you have no idea what i was talking about.
The clock won't change from what's fed into the damn chip, not the clock won't change from what was written. You claimed it'd use prescalers and whatnot. It won't.
no it is you that dont get it. in fact it is your post that started it that i need to rectify.... and i and you was not talking anything yet about filtering. analog filtering is entirely a different story...
"Entirely a different story"? What exactly are you talking about? What are you trying to prove with your posts so far about the values that the DAC may or may not output? That it's not going to give a good sine? Because - that's exactly what the analog filtering is there for. After this filtering, the sine
will be "perfect".
This whole thing started with the notion that this particular DDS module can dump out a decent 30Mhz.
Oh really? Let me refresh your memory:
Even with filtering, point is that those modules generally use a 125Mhz xtal. 30Mhz sine wave with a 125Mhz MCLK will give a guy, what, 4.x bits of DAC resolution, give or take...
As far as filtering goes... Sure...design all the filters you want. Try it at 30Mhz and you'll end up with garbage. Even if you do get a decent sine wave output that's free of distortion, it'll likely only work well within a very narrow set of parameters.
You have to add to the accumulator a number that'll swing the DAC fast enough to give you that 30Mhz output, and it has to be a large number. As the desired output frequency gets higher, the number of 'steps' in your output drops.
What's this talk about 4 bits? 2 bits? "Even with filtering", etc etc. You stated it's not possible to get a good sine out of this AD9850, "even with filtering". You also made it very clear that you don't know what filtering can do, focusing instead on irrelevant things like "the number of steps", like this makes any difference after filtering...
With all values normalized to 1, fc = 1.3 MHz, f = 164 kHz.
f/fc = 0.126154 - this is the frequency tuning word.
one question.... where did you get the 1.3MHz?
"Entirely a different story"? What exactly are you talking about? What are you trying to prove with your posts so far about the values that the DAC may or may not output? That it's not going to give a good sine? Because - that's exactly what the analog filtering is there for. After this filtering, the sine will be "perfect".
yes, but because i guess you are too particular about 2 bits or 10 bits arguments. in fact how many bits doesn't really matter if the filtering is robust enough to take care all the sampling rate (stair steps) possibilities. when you were arguing the 10 bits argument, i thought you are saying... at 30MHz, the DDS will have 10 bits output resolutions (1024 varying values or sine phase and all) which is not the case.
otoh, on the analog filtering side, i'm not the expert but eliminating "stairsteps" is straight forward if at one particular "output sampling speed or freq" but it will obscure me for various stairsteps possibilities. what i can see, a good filtering will need to be able to diminish all "stairsteps". if one is not clear what i'm talking about... there is stairsteps at 125MHz sampling speed, ie 8ns of where you can put your feet on. and then there is a stairsteps at 1MHz, ie 1us of where you can put your feet on (the flat horizontal space on the scope), they both have very broad or different harmonics or bw that you are trying to eliminate, that i'm not sure how. if one is to eliminate harmonics at 1MHz output sampling, then it will diminish DDS higher freq output signal (overly low-pass), but if one is to perfectly eliminates harmonics at 30MHz FG output (that is maybe around 125MHz of sampling frequency), the filter wont eliminates stairsteps at lower sampling rate of 1MHz. as i said i'm not the expert and i dont tend to talk about it.
somehow filtering will be related to the "output sampling rate", and thats changing, i believe we are all already in agreement with that and proven in hamsters image.
Many DDS devices, including full signal generators, just leave the stairsteps at the lower frequencies - they end up being so small they don't have much effect. If I were designing one, I'd investigate a network of switched filters (not switching filters, mind you) to adapt to different frequencies, but it's often decided to be unnecessary.
One can also run the process backwards:
1. Draw the desired sine wave to a paper.
2. "sample" the sine wave at desired sample rate and record the sine wave's amplitude at each sample instance.**
3. Perform a simple quantization ie. convert the samples to signed integer values.
Now you should have sampled the original sine wave. Let's do the same thing that the DDS is doing in order to get back to the sine wave:
4. Recreate the sampled sine wave by plotting the integer values to the paper.
5. Apply the zero-oder hold which corresponds to a DAC. You should get the familiar stair-case waveform.
6. Apply a reconstruction filter ie. connect the DAC output samples with a smooth curve.* The reconstruction filter will remove all staircase components and the resulting output signal will be a smooth sine wave.
*See also
http://en.wikipedia.org/wiki/Zero-order_hold and how the frequency response will have a 3.9224 dB roll-off at Nyquist frequency (Half the sampling frequency). This may be need to be compensated if the output frequency near the Nyquist frequency. One way to compensate this droop is to create a reconstruction filter which will have an inverted frequency response compared to the zero-order hold, thus emphasizing the frequency components near the Nyquist frequency by 3.9224 dB.
** Particularily at lower frequencies it is very easy to see the more quantization steps you have (10 bits vs 4 bits, for example) the better the quantizited signal will match to the original analog signal. The difference between the original signal and the quantizated sample value is called quantization error which will manifest itself as noise at the DDS output signal.
yes, but because i guess you are too particular about 2 bits or 10 bits arguments. in fact how many bits doesn't really matter if the filtering is robust enough to take care all the sampling rate (stair steps) possibilities. when you were arguing the 10 bits argument, i thought you are saying... at 30MHz, the DDS will have 10 bits output resolutions (1024 varying values or sine phase and all) which is not the case.
I think you may need to read post #34 again. You seem confused about bit depth vs. sampling rate. The DAC is 10 bits. You may only ever see 2 values at a high frequency, but those 2 values can still be any of 1024 (10 bits) values. I said that in post #27. And the two values
contain enough information to reproduce the perfect sine(!) after filtering. Something Skimask is still failing to grasp
I think you may need to read post #34 again. You seem confused about bit depth vs. sampling rate. The DAC is 10 bits. You may only ever see 2 values at a high frequency, but those 2 values can still be any of 1024 (10 bits) values. I said that in post #27. And the two values contain enough information to reproduce the perfect sine(!) after filtering. Something Skimask is still failing to grasp
he got sensical points its just he's barking on the wrong tree, and your argument about audiophoolery are valid too.... except the bolded one above... i believe we are talking the same thing, so do i with some of skymask's points... 2 values whatever it is, contain informations, it is agreed. but what information it is, is irrelevant, as long as we have 2 differing points, we are able to construct sine (with proper filtering).