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The art of logic signal manipulation with analogue components (D/R/C)
Posted by max.wwwang on 27 Feb, 2023 07:33 -
[Original title: Please help figure out what's going on here]
Can someone experienced in digital circuits please help me understand what the tricks here are. It's part of a digital circuit; its interaction with the world outside it is all digital (LOWs and HIGHs). This is fine. But in this little part, I find it very difficult to understand the function of the resistors and diodes in the areas [1] and [2].
This is drawn up by myself based on a circuit board of my repair project, which I carefully checked many times so it should be correct. Simply because I don't understand what's going on here, chances are the components are arranged in a very bad way which might otherwise be much more revealing and intuitive!
[Edit] Have added a tidier (I think) version. Both are the same thing.
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Well R80 and D7 will increase the pull to ground (extra to what R81 does) if the right side of the capacitor goes negative.
So it seems to be protection so changing states on the capacitor C22 cannot try to pull the input of U9C below ground and damage it.
Seems kind of unlikely through with 220k in series but maybe it's just there to stop the cap charging up negative because that causes some other problem, like a slower response when it changes to high.
D5 appears to be changing how much current feeds into the RN7C filter network when the input voltage is above 0.7V.
Might be to prevent a LOW signal from discharging C20 since it will have to discharge through the 220K. But a HIGH can go through the diode (less 0.7V and charge C20 quicker.
Just guessing though, I dunno exactly what that thing does -
Well R80 and D7 will increase the pull to ground (extra to what R81 does) if the right side of the capacitor goes negative.
It is also what I thought is possibly the only use of D7. But as you said, can this be possible (and it requires the negative voltage to be less than -0.6V or so for D7 to be useful)? Possibly yes ...
So it seems to be protection so changing states on the capacitor C22 cannot try to pull the input of U9C below ground and damage it.
Seems kind of unlikely through with 220k in series but maybe it's just there to stop the cap charging up negative because that causes some other problem, like a slower response when it changes to high.D5 appears to be changing how much current feeds into the RN7C filter network when the input voltage is above 0.7V.
Find it hard to get my head around here.
Might be to prevent a LOW signal from discharging C20 since it will have to discharge through the 220K. But a HIGH can go through the diode (less 0.7V and charge C20 quicker.
Just guessing though, I dunno exactly what that thing does
At first I think we can ignore C20 and C21 since they appear to be just 'standard' capacitors that exist everywhere near any chip (I understand they are for noise filtering, for example). It's just C22 that seems a real deal because it's in serial with the line, not bypassing. But physically they three are all the same puppy (same look, same physical size), though I'm not sure if they have the identical capacitance. -
The resistors and diodes around C20 and C22 are delay networks. Low to high transitions are delayed less than high to low. C22 with resistors and diode form a short pulse when the preceding U11B changes state. The input to U9C will return to low even if the output of U11B remains high.
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The resistors and diodes around C20 and C22 are delay networks. Low to high transitions are delayed less than high to low. C22 with resistors and diode form a short pulse when the preceding inverter changes state.
That's very specific and interesting! I may possibly set up a minimal circuit to demonstrate this. (Or perhaps the easiest way is simply to probe these pins!)
For the second bit, I presume it applies only on one side of the pulse on the output pin of U11B? Is it like an overshoot on the falling edge?
Anyway, I'm convinced that these passive components are essentially all for the tweaking of the signal, be it delay, push, sharpen, strengthen, dampen, or whatever. -
The way I see it is that the whole circuit is set up to be edge sensitive. It depends on the rest of the circuit as to why they did it this way.
If you have the board this is on, in a working state, then sure you could probe it to see what is happening.
The RC filters in the first section cause a delay between one input of the NAND or NOR gates connected to the input signal. This can be used to create pulsed signals. The so called differentiator or high pass filter in the second stage does this to. On a low to high change on the output of U11B the signal after the capacitor will go high and then slowly decay to low again, based on the RC time given by C22 and R81. When the output of U11B changes from high to low the signal after the capacitor goes below ground level and will then increase more rapidly based on the RC time given by C22 and the combination of the series resistance of R80 and D7 parallel to R81.
The diodes in the first section bring different delays for low to high and high to low signal changes. -
The way I see it is that the whole circuit is set up to be edge sensitive. It depends on the rest of the circuit as to why they did it this way.
Thanks. That's very helpful.
If you have the board this is on, in a working state, then sure you could probe it to see what is happening.
The RC filters in the first section cause a delay between one input of the NAND or NOR gates connected to the input signal. This can be used to create pulsed signals. The so called differentiator or high pass filter in the second stage does this to. On a low to high change on the output of U11B the signal after the capacitor will go high and then slowly decay to low again, based on the RC time given by C22 and R81. When the output of U11B changes from high to low the signal after the capacitor goes below ground level and will then increase more rapidly based on the RC time given by C22 and the combination of the series resistance of R80 and D7 parallel to R81.
The diodes in the first section bring different delays for low to high and high to low signal changes.
Yes, I have the board with this part of circuit, which is a part of my repair project. And true, its working almost entirely relies on the pulses, either falling or rising, and their timing and synchronisation, etc. I hope this part is working so I can probe around and have a visual appreciation of the function of these parts (if not working, I'm striving to bring it back up and running).
Are you able to comment on the function of R78 on the top, tieing up the output and input pins of two gates in one continuous signal path? I came across this and had this question before. Thanks.
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I'm no expert on this, but think it acts as some sort of positive feedback. It might change the charging and discharging rate of C21 in some way.
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I'm no expert on this, but think it acts as some sort of positive feedback. It might change the charging and discharging rate of C21 in some way.
Yes, positive feedback, as it appears!
What still baffles me is that, these are not analogue components (such as op-amps, where feedback is common) but logic ones. They don't quite care too much about the slight difference in voltage as long as they are well above or below the threshold differentiating HIGH and LOW. -
I'm no expert on this, but think it acts as some sort of positive feedback. It might change the charging and discharging rate of C21 in some way.
The primary function of R78 is not to alter C21 charge or discharge rate.
The positive feedback provided by R78 gives a Schmitt trigger characteristic to the U9E inverter. The RC delay components convert the step waveform at the N1-3D-4 input to an exponential one, ie a relatively slowly rising or falling waveform. If R78 were not present, at some point this waveform would cross the threshold of the inverter input and cause its output to toggle. However the slowly changing input makes it sensitive to noise so the inverter output might not be a single transition but instead a few fast toggles before reaching steady state. With R78 providing a small amount of positive feedback the exponential waveform receives a small addition if rising (and subtraction if falling) so that once the threshold is crossed the inverter output toggles cleanly just once. -
D5 shortens the delay for positive-going input, compared to the long delay through all the resistors for negative-going input.
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Thanks wasedadoc and TimFox. I've added a tidier version above.
That all makes good sense. If I understand correctly, these R/D/C components only either slightly modify the signal or help the gates work more 'cleanly', but do not change the HIGHs or LOWs of the signal by, say, turning things up side down.
If this is the case, looking at the upper half, it appears to me the output on N1-4D-11 will always be LOW regardless of the input signal on N1-3D-4, because the two inputs to U18D will always be one HIGH the other LOW. Then what's the point here?
It is possible that, due to the delays such as by softening the rising or falling of the signal, i.e. the change of the timing of the rises and falls (with reference to the HIGH/LOW threshold), there might also be HIGH outputs on N1-4D-11 (i.e. a square wave signal). If this is correct, then the values of these R/D/C components would have required a careful calculation and tuning by the designer. This is not unlikely because of the existence of the pod (R73), which allows adjustments by end user.
For the lower half, what will be the initial status of U11B pin 5 be if I want to mentally 'simulate' its working (suppose its pin 6 is HIGH)?
[Edit] This is not a question --- it should be LOW at the beginning because of its connection to GND.
I will see if I can confirm these on a scope if this part of the circuit is working.
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The right half of the lower part, consisting of U9C, U9D, and U11B, appears to be essentially an inverter, probably with some tricky tweaking (of timing) of the input signal.
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If this is the case, looking at the upper half, it appears to me the output on N1-4D-11 will always be LOW regardless of the input signal on N1-3D-4, because the two inputs to U18D will always be one HIGH the other LOW.
You should learn to draw timing diagrams. Your conclusion about the output of U81D is incorrect.
Start with the input N1-3D-4 being HIGH and the inverter output LOW. The NOR output will be LOW. Now make N1-3D-4 go LOW. The direct input to the NOR gate goes LOW imediately. But its other input remains LOW for some time because of the RC delay to the inverter input. So there is a period when both of the NOR inputs are LOW which makes its output HIGH. The variable resistor allows adjustment of that pulse width. -
Start with the input N1-3D-4 being HIGH and the inverter output LOW. The NOR output will be LOW. Now make N1-3D-4 go LOW. The direct input to the NOR gate goes LOW imediately. But its other input remains LOW for some time because of the RC delay to the inverter input. So there is a period when both of the NOR inputs are LOW which makes its output HIGH. The variable resistor allows adjustment of that pulse width.
Yes, I get that. Thanks. -
When the N1-3D-4 input goes HIGH again the diode lets the capacitor charge up at a much faster rate than it discharged so the circuit returns to the initial state of my preceding post quite quickly to be ready for the next HIGH to LOW transition of the N1-3D-4 input.
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In another similar, but simpler, case (RHS of the circuit), I think the output on N2-6B-4 and N2-6B-11, based on the ON/OFF status of the transistor, will be like, roughly, as shown in the timing diagram.
[Edit] Capacitors are not specified. I'm assuming they are identical.
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Ha, another failure of the image system. When I click on the timing diagram I get another image.
But yes the exclusive or gate 2-6B-C will detect the state of the transistor.Code: [Select]XOR
0 0 ==> 0
0 1 ==> 1
1 0 ==> 1
0 0 ==> 0
But again there is some pulse forming done with the other gates and the RC filters. Which seem to be in your timing diagram, but hard to see if it lines up without the big version of it.
Edit: Found the relating image in another thread. (here) -
Thanks.
I was aware of the XOR operation, and used it in deriving the diagram.
It's not clear to me in your response. Do you think my diagram is largely correct?
By the way, I'm no expert, but I think the R/C part is probably not working as a filter here? -
I'm still looking at the signals
The RC setup here constitutes a low pass filter. Only the -3dB point is fairly low. So to me, but also not an expert, it is a filter.
Edit: The timing diagram looks ok, but it might be that the timings on the inputs 2-6B-1 and 2-6B-2 are the other way round. This depends on the values of the two capacitors. But assuming they are the same the delay on 2-6B-1 will be longer due to R32 being 10K, and R34 only 2K2. The actual times can be calculated but the value of the cap needs to be known. -
You are right. I took it as 2k2 > 10k in making the diagram.
Yes, 2-2B-1 and 2 should be the other way round in terms of the amount of delay. Thanks.
So my guess here is that the two outputs are one normal H the other normal L (which may be taken as L active or H active, respectively, for their downstream users), but both will send a pulse (the width probably does not matter) when a change of state of the transistor is detected (from ON to OFF or the other way round). And there is a timing difference between these two pulses.
Why it is so will need more investigation. Thanks! -
By the way, I'm no expert, but I think the R/C part is probably not working as a filter here?
Correct. Both R32&C and R34&C are to make delays, not to act as filters. -
I've added the correct version of the timing diagram. Note --- for illustration purpose, it's only the order of events that matters, not the actual pulse width. See picture "sync".
For simplicity, in this case, it's assumed that the input pulse width is always wide enough for the delayed signals to transit.
To add a bit fun, I've looked into what it looks like if without such condition, i.e. if the input pulse width may not be wide enough for the delayed signal to flip. This is in diagram "sync-1".
These timing diagrams are all created 'programmatically' with Excel. Arbitrary input signal is created with random number generator. Timing diagrams are drawn automatically with conditional format. For those interested, I've also attached the Excel spreadsheet for this. There is no guarantee it will work as intended on your machine (this is far from uncommon for M$ products).
On my machine, pressing Shift-Alt-Ctrl F9 will cause the spreadsheet to 'recalculate' and change randomly the input signal and, of course, the output signals.
[Edit] A bug in the formulas fixed. Diagrams updated.
[More edit] The Excel file has been taken off due to an obvious lack of interest, or abundance of caution (which is good), or both.
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Now how the D/R/C components work in between the gates in the circuits of the original post is crystal clear to me. I also now understand how R78 (in the original post) works as feedback (just like feedback of op-amps), though haven't yet got into the very detail. When you know, it's so simple. Good learning!
Thanks to the experts! 
Timing diagrams for those can also easily be made. Will do when time allows, or when my repair (reverse engineering) project comes to that point. -
By the way, I'm no expert, but I think the R/C part is probably not working as a filter here?
Correct. Both R32&C and R34&C are to make delays, not to act as filters.
To be precise the setup in combination with the gates is what gives the signal its delay. The R/C combination is still a low pass filter. Just look at the signals on the capacitor and see how the edge of the signal is filtered into a slope.
Also when you raise the frequency of the input signal it will reach a point that the circuit does not work anymore.
Added an image plucked from the net to show this filtering.