Thanks for your help!
My mistake the "b" 2 "B" makes things 8 times harder
Well, my application has a few floating point, and a pretty amount of code. I don't yet know how much cause I've to first write the container for the application, so decide the architecture, then I can write the C code.
The code will implement a "controllable" PID system that do some math on the 32 channels @ 24 bit from ADC and output 32 channels @ 16 bit to DAC. The application also has to compute the target point signal, then compare the feedback signal coming from the ADC, and output the PID error checked signal to DAC.
There is also some logic around this (as example it can be that the feedback for a PID may come from ADC signal 1 + ADC signal 2), or PID setting can change after X seconds of execution.. and so on.
It's not that simple.
It also has 64 digital bit input and output to be managed by the software.
In addition to the ADC / DAC / GPIO signals there are also another slow async stream: the command stream. Commands are received from the Gigabit interface driven in verilog. They passthrough to the SoC and setup the way the application work (like command #10 with payload 144 can mean set the P for line 1 of the application at 1.44). Commands are 128bit long payload, and can even go out from the SoC (like as example command #14 with payload 55 can mean error number 55 in the application).
One last requirements, the application should be loaded and executed in place (XIP). I mean it would be better if one can load the application through the verilog gigabit interface to some ROM, then the SoC could execute the application from the SoC. If this is a blocking requirements, I have to think about this.
The doubt I have and suggestion I need for this application are:
- bandwidth requirements and system frequency, as I tell you 10kHz is a good reach point, 100kHz (so 96Mbytes/sec almost) is the dream point
- floating point and speed of computation. Consider that each input ADC signal has to be computed in time with the system frequency (10kHz as example), so that the signal to DAC is output before the next 10kHz tick
- XIP executable application mode, is it feasible?
Hope I've explain my use case. I think I need an hardcore SoC, but I don't know.