DDR3 is as simple to run as DDR2, DDR except for the different power-up settings and a few new commands and # of clock cycles. Maybe a punishment for not writing your own HDMI transmitter would be writing your own DDR3.sv. Micron does have a DDR3 Verilog testbench code which was designed to validate/verify functionality of your DDR3.sv controller which you can run in ModelSim. Sorta like my testbench code which drives and tests the 3 Geometry unit sections wired together to render an output.
That double extra LUT and gates is not from the ZQ CALIBRATION Long and Short pattern generator, or for it's timeout timer.
That double extra LUT and gates is not from the ZQ CALIBRATION Long and Short pattern generator, or for it's timeout timer.Then what it is?
My point is I think you are trying to bite more than you can chew. To my knowledge, HW-agnostic DDR3 controller does not exist at this point, and there's got to be a reason for it.
Speaking of which - I have tried generating UniPHY-based DDR3 controller for MAX10 device (for the DECA boards I received today), and generator failed with some cryptic messages. Before I tried doing it for CV with the same results - it generates "something", but ultimately fails so I don't really know if whatever it's generated is usable or not. I've been using the most recent Quartus Lite version (20.1.1 I think) just to be sure.
There is no way running a 800MHz ram chip at 400MHz will make enough heat in the chip or your FPGA to throw out the timing by over over 500ps on a 800MHz ram chip with 1600mtps.
As for the Quartus, if the DDR3 compiler give you a weird 'ERROR, like unfound linux command during generation', Nockieboy finally got his to compile. The DDR3 generator needs Linux runtime/command shell environment for Win10 installed with an added 'path' setting in the system. You would have to ask him as I'm still on Win7 and cannot use the latest Quartus ram compiler.
but the effect is there, and can cause issues if your design is marginal to begin with.
Sorry, it's not a path, but bash which needs to be installed. Discussion here:
https://community.intel.com/t5/Intel-Quartus-Prime-Software/DDR3-megawizard-generation-error-in-Quartus-20-1/td-p/1244332
Info: DDR3C: Variation language : Verilog
Info: DDR3C: Output directory : D:\Andrey\Projects\Altera\DECA_DDR
Info: DDR3C: Generating variation file D:\Andrey\Projects\Altera\DECA_DDR\DDR3C.v
Info: DDR3C: Generating synthesis files
<html>Info: Generating <b>altera_mem_if_ddr3_emif</b> "<b>DDR3C</b>" for QUARTUS_SYNTH
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_emif</b> "<b>DDR3C</b>"
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_pll</b> "<b>pll0</b>"
Info: Generating clock pair generator
Info: Generating altgpio
Info:
Info: *****************************
Info:
Info: Remember to run the DDR3C_p0_pin_assignments.tcl
Info: script after running Synthesis and before Fitting.
Info:
Info: *****************************
Info:
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_phy_core</b> "<b>p0</b>"
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_afi_mux</b> "<b>m0</b>"
Error: Error during execution of "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: Execution of command "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: /mnt/c/intelfpga_lite/20.1/quartus/bin64/uniphy_mcc.exe -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../DDR3C_s0_AC_ROM.hex -inst_rom ../DDR3C_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001000010001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100010000 -DAC_ROM_MR1=0000001000100 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0000000000000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001000001001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001010001000 -DAC_ROM_MR1_MIRR=0000000100100 -DAC_ROM_MR2_MIRR=0000000000000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=1 -DFULL_RATE=0 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0
Error: UniPHY Sequencer Microcode Compiler
Error: Copyright (C) 2020 Intel Corporation. All rights reserved.
Error: Info: Reading sequencer_mc/ac_rom.s ...
Error: Info: Reading sequencer_mc/inst_rom.s ...
Error: Info: Writing ../DDR3C_s0_AC_ROM.hex ...
Error: Info: Writing ../DDR3C_s0_inst_ROM.hex ...
Error: Info: Writing sequencer/sequencer_auto_ac_init.c ...
Error: Info: Writing sequencer/sequencer_auto_inst_init.c ...
Error: Info: Writing sequencer/sequencer_auto.h ...
Error: Info: Writing sequencer/sequencer_auto.h ...
Error: Info: Writing ../sequencer_auto_h.sv ...
Error: Info: Microcode compilation successful
Error: /mnt/c/intelfpga_lite/20.1/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE
Error: nios2-bsp: Using /mnt/c/intelfpga_lite/20.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl to set system-dependent settings.
Error: nios2-bsp: Updating existing BSP because sequencer_bsp/settings.bsp exists.
Error: nios2-bsp: Using SOPC design file ../pre_compile.sopcinfo found in ..
Error: nios2-bsp: Running "nios2-bsp-update-settings --settings sequencer_bsp/settings.bsp --bsp-dir sequencer_bsp --sopc ../pre_compile.sopcinfo --script /mnt/c/intelfpga_lite/20.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl default_sections_mapping sequencer_mem use_bootloader DONT_CHANGE "
Error: child process exited abnormally
Error: Cannot find sequencer/sequencer.elf
<html>Error: An error occurred<br> while executing<br>"error "An error occurred""<br> (procedure "_error" line 8)<br> invoked from within<br>"_error "Cannot find $seq_file""<br> ("if" then script line 2)<br> invoked from within<br>"if {[file exists $seq_file] == 0} {<br> _error "Cannot find $seq_file"<br> }"<br> (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)<br> invoked from within<br>"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""<br> invoked from within<br>"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"<br> ("if" then script line 2)<br> invoked from within<br>"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {<br> set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."<br> (procedure "generate_qsys_sequencer_sw" line 943)<br> invoked from within<br>"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..."<br> invoked from within<br>"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..."<br> ("if" else script line 2)<br> invoked from within<br>"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {<br> set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."<br> (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)<br> invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"<br> invoked from within<br>"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"<br> (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)<br> invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH"<br> invoked from within<br>"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH] {<br> set file_name [file tail $genera..."<br> (procedure "generate_synth" line 8)<br> invoked from within<br>"generate_synth DDR3C_s0"
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_qseq</b> "<b>s0</b>"
Error: Generation stopped, 1 or more modules remaining
<html>Info: Done "<b>DDR3C</b>" with 7 modules, 29 files
Info: DDR3C: Generating simulation model
<html>Info: Generating <b>altera_mem_if_ddr3_emif</b> "<b>DDR3C</b>" for SIM_VERILOG
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_emif</b> "<b>DDR3C</b>"
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_pll</b> "<b>pll0</b>"
Info: Generating clock pair generator
Info: Generating altgpio
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_phy_core</b> "<b>p0</b>"
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_afi_mux</b> "<b>m0</b>"
Error: Error during execution of "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: Execution of command "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: /mnt/c/intelfpga_lite/20.1/quartus/bin64/uniphy_mcc.exe -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../DDR3C_s0_AC_ROM.hex -inst_rom ../DDR3C_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001000010001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100010000 -DAC_ROM_MR1=0000001000100 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0000000000000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001000001001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001010001000 -DAC_ROM_MR1_MIRR=0000000100100 -DAC_ROM_MR2_MIRR=0000000000000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=1 -DFULL_RATE=0 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0
Error: UniPHY Sequencer Microcode Compiler
Error: Copyright (C) 2020 Intel Corporation. All rights reserved.
Error: Info: Reading sequencer_mc/ac_rom.s ...
Error: Info: Reading sequencer_mc/inst_rom.s ...
Error: Info: Writing ../DDR3C_s0_AC_ROM.hex ...
Error: Info: Writing ../DDR3C_s0_inst_ROM.hex ...
Error: Info: Writing sequencer/sequencer_auto_ac_init.c ...
Error: Info: Writing sequencer/sequencer_auto_inst_init.c ...
Error: Info: Writing sequencer/sequencer_auto.h ...
Error: Info: Writing sequencer/sequencer_auto.h ...
Error: Info: Writing ../sequencer_auto_h.sv ...
Error: Info: Microcode compilation successful
Error: /mnt/c/intelfpga_lite/20.1/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE
Error: nios2-bsp: Using /mnt/c/intelfpga_lite/20.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl to set system-dependent settings.
Error: nios2-bsp: Updating existing BSP because sequencer_bsp/settings.bsp exists.
Error: nios2-bsp: Using SOPC design file ../pre_compile.sopcinfo found in ..
Error: nios2-bsp: Running "nios2-bsp-update-settings --settings sequencer_bsp/settings.bsp --bsp-dir sequencer_bsp --sopc ../pre_compile.sopcinfo --script /mnt/c/intelfpga_lite/20.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl default_sections_mapping sequencer_mem use_bootloader DONT_CHANGE "
Error: child process exited abnormally
Error: Cannot find sequencer/sequencer.elf
<html>Error: An error occurred<br> while executing<br>"error "An error occurred""<br> (procedure "_error" line 8)<br> invoked from within<br>"_error "Cannot find $seq_file""<br> ("if" then script line 2)<br> invoked from within<br>"if {[file exists $seq_file] == 0} {<br> _error "Cannot find $seq_file"<br> }"<br> (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)<br> invoked from within<br>"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""<br> invoked from within<br>"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"<br> ("if" then script line 2)<br> invoked from within<br>"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {<br> set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."<br> (procedure "generate_qsys_sequencer_sw" line 943)<br> invoked from within<br>"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..."<br> invoked from within<br>"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..."<br> ("if" else script line 2)<br> invoked from within<br>"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {<br> set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."<br> (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)<br> invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"<br> invoked from within<br>"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"<br> (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)<br> invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir SIM_VERILOG"<br> invoked from within<br>"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir SIM_VERILOG] {<br> set file_name [file tail $generate..."<br> (procedure "generate_verilog_sim" line 7)<br> invoked from within<br>"generate_verilog_sim DDR3C_s0"
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_qseq</b> "<b>s0</b>"
Error: Generation stopped, 1 or more modules remaining
<html>Info: Done "<b>DDR3C</b>" with 7 modules, 21 files
Info: Generated simulation scripts for Modelsim in D:/Andrey/Projects/Altera/DECA_DDR/DDR3C_sim/mentor directory.
Info: Generated simulation scripts for VCS and VCS MX in D:/Andrey/Projects/Altera/DECA_DDR/DDR3C_sim/synopsys directory.
Info: Generated simulation scripts for NCSIM in D:/Andrey/Projects/Altera/DECA_DDR/DDR3C_sim/cadence directory.
Info: Generated simulation scripts for Riviera-PRO in D:/Andrey/Projects/Altera/DECA_DDR/DDR3C_sim/aldec directory.
Sorry, it's not a path, but bash which needs to be installed. Discussion here:
https://community.intel.com/t5/Intel-Quartus-Prime-Software/DDR3-megawizard-generation-error-in-Quartus-20-1/td-p/1244332Did all of that - still doesn't work:Code: [Select]Info: DDR3C: Variation language : Verilog
Info: DDR3C: Output directory : D:\Andrey\Projects\Altera\DECA_DDR
Info: DDR3C: Generating variation file D:\Andrey\Projects\Altera\DECA_DDR\DDR3C.v
Info: DDR3C: Generating synthesis files
<html>Info: Generating <b>altera_mem_if_ddr3_emif</b> "<b>DDR3C</b>" for QUARTUS_SYNTH
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_emif</b> "<b>DDR3C</b>"
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_pll</b> "<b>pll0</b>"
Info: Generating clock pair generator
Info: Generating altgpio
Info:
Info: *****************************
Info:
Info: Remember to run the DDR3C_p0_pin_assignments.tcl
Info: script after running Synthesis and before Fitting.
Info:
Info: *****************************
Info:
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_phy_core</b> "<b>p0</b>"
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_afi_mux</b> "<b>m0</b>"
Error: Error during execution of "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: Execution of command "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: /mnt/c/intelfpga_lite/20.1/quartus/bin64/uniphy_mcc.exe -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../DDR3C_s0_AC_ROM.hex -inst_rom ../DDR3C_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001000010001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100010000 -DAC_ROM_MR1=0000001000100 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0000000000000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001000001001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001010001000 -DAC_ROM_MR1_MIRR=0000000100100 -DAC_ROM_MR2_MIRR=0000000000000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=1 -DFULL_RATE=0 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0
Error: UniPHY Sequencer Microcode Compiler
Error: Copyright (C) 2020 Intel Corporation. All rights reserved.
Error: Info: Reading sequencer_mc/ac_rom.s ...
Error: Info: Reading sequencer_mc/inst_rom.s ...
Error: Info: Writing ../DDR3C_s0_AC_ROM.hex ...
Error: Info: Writing ../DDR3C_s0_inst_ROM.hex ...
Error: Info: Writing sequencer/sequencer_auto_ac_init.c ...
Error: Info: Writing sequencer/sequencer_auto_inst_init.c ...
Error: Info: Writing sequencer/sequencer_auto.h ...
Error: Info: Writing sequencer/sequencer_auto.h ...
Error: Info: Writing ../sequencer_auto_h.sv ...
Error: Info: Microcode compilation successful
Error: /mnt/c/intelfpga_lite/20.1/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE
Error: nios2-bsp: Using /mnt/c/intelfpga_lite/20.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl to set system-dependent settings.
Error: nios2-bsp: Updating existing BSP because sequencer_bsp/settings.bsp exists.
Error: nios2-bsp: Using SOPC design file ../pre_compile.sopcinfo found in ..
Error: nios2-bsp: Running "nios2-bsp-update-settings --settings sequencer_bsp/settings.bsp --bsp-dir sequencer_bsp --sopc ../pre_compile.sopcinfo --script /mnt/c/intelfpga_lite/20.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl default_sections_mapping sequencer_mem use_bootloader DONT_CHANGE "
Error: child process exited abnormally
Error: Cannot find sequencer/sequencer.elf
<html>Error: An error occurred<br> while executing<br>"error "An error occurred""<br> (procedure "_error" line 8)<br> invoked from within<br>"_error "Cannot find $seq_file""<br> ("if" then script line 2)<br> invoked from within<br>"if {[file exists $seq_file] == 0} {<br> _error "Cannot find $seq_file"<br> }"<br> (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)<br> invoked from within<br>"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""<br> invoked from within<br>"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"<br> ("if" then script line 2)<br> invoked from within<br>"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {<br> set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."<br> (procedure "generate_qsys_sequencer_sw" line 943)<br> invoked from within<br>"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..."<br> invoked from within<br>"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..."<br> ("if" else script line 2)<br> invoked from within<br>"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {<br> set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."<br> (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)<br> invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"<br> invoked from within<br>"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"<br> (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)<br> invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH"<br> invoked from within<br>"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH] {<br> set file_name [file tail $genera..."<br> (procedure "generate_synth" line 8)<br> invoked from within<br>"generate_synth DDR3C_s0"
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_qseq</b> "<b>s0</b>"
Error: Generation stopped, 1 or more modules remaining
<html>Info: Done "<b>DDR3C</b>" with 7 modules, 29 files
Info: DDR3C: Generating simulation model
<html>Info: Generating <b>altera_mem_if_ddr3_emif</b> "<b>DDR3C</b>" for SIM_VERILOG
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_emif</b> "<b>DDR3C</b>"
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_pll</b> "<b>pll0</b>"
Info: Generating clock pair generator
Info: Generating altgpio
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_phy_core</b> "<b>p0</b>"
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_afi_mux</b> "<b>m0</b>"
Error: Error during execution of "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: Execution of command "{C:/intelfpga_lite/20.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: /mnt/c/intelfpga_lite/20.1/quartus/bin64/uniphy_mcc.exe -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../DDR3C_s0_AC_ROM.hex -inst_rom ../DDR3C_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0001000010001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100010000 -DAC_ROM_MR1=0000001000100 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0000000000000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001000001001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001010001000 -DAC_ROM_MR1_MIRR=0000000100100 -DAC_ROM_MR2_MIRR=0000000000000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=1 -DFULL_RATE=0 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0
Error: UniPHY Sequencer Microcode Compiler
Error: Copyright (C) 2020 Intel Corporation. All rights reserved.
Error: Info: Reading sequencer_mc/ac_rom.s ...
Error: Info: Reading sequencer_mc/inst_rom.s ...
Error: Info: Writing ../DDR3C_s0_AC_ROM.hex ...
Error: Info: Writing ../DDR3C_s0_inst_ROM.hex ...
Error: Info: Writing sequencer/sequencer_auto_ac_init.c ...
Error: Info: Writing sequencer/sequencer_auto_inst_init.c ...
Error: Info: Writing sequencer/sequencer_auto.h ...
Error: Info: Writing sequencer/sequencer_auto.h ...
Error: Info: Writing ../sequencer_auto_h.sv ...
Error: Info: Microcode compilation successful
Error: /mnt/c/intelfpga_lite/20.1/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE
Error: nios2-bsp: Using /mnt/c/intelfpga_lite/20.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl to set system-dependent settings.
Error: nios2-bsp: Updating existing BSP because sequencer_bsp/settings.bsp exists.
Error: nios2-bsp: Using SOPC design file ../pre_compile.sopcinfo found in ..
Error: nios2-bsp: Running "nios2-bsp-update-settings --settings sequencer_bsp/settings.bsp --bsp-dir sequencer_bsp --sopc ../pre_compile.sopcinfo --script /mnt/c/intelfpga_lite/20.1/nios2eds/sdk2/bin/bsp-set-defaults.tcl default_sections_mapping sequencer_mem use_bootloader DONT_CHANGE "
Error: child process exited abnormally
Error: Cannot find sequencer/sequencer.elf
<html>Error: An error occurred<br> while executing<br>"error "An error occurred""<br> (procedure "_error" line 8)<br> invoked from within<br>"_error "Cannot find $seq_file""<br> ("if" then script line 2)<br> invoked from within<br>"if {[file exists $seq_file] == 0} {<br> _error "Cannot find $seq_file"<br> }"<br> (procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)<br> invoked from within<br>"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""<br> invoked from within<br>"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"<br> ("if" then script line 2)<br> invoked from within<br>"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {<br> set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."<br> (procedure "generate_qsys_sequencer_sw" line 943)<br> invoked from within<br>"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..."<br> invoked from within<br>"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..."<br> ("if" else script line 2)<br> invoked from within<br>"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {<br> set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."<br> (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)<br> invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"<br> invoked from within<br>"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"<br> (procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)<br> invoked from within<br>"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir SIM_VERILOG"<br> invoked from within<br>"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir SIM_VERILOG] {<br> set file_name [file tail $generate..."<br> (procedure "generate_verilog_sim" line 7)<br> invoked from within<br>"generate_verilog_sim DDR3C_s0"
<html>Info: "<b>DDR3C</b>" instantiated <b>altera_mem_if_ddr3_qseq</b> "<b>s0</b>"
Error: Generation stopped, 1 or more modules remaining
<html>Info: Done "<b>DDR3C</b>" with 7 modules, 21 files
Info: Generated simulation scripts for Modelsim in D:/Andrey/Projects/Altera/DECA_DDR/DDR3C_sim/mentor directory.
Info: Generated simulation scripts for VCS and VCS MX in D:/Andrey/Projects/Altera/DECA_DDR/DDR3C_sim/synopsys directory.
Info: Generated simulation scripts for NCSIM in D:/Andrey/Projects/Altera/DECA_DDR/DDR3C_sim/cadence directory.
Info: Generated simulation scripts for Riviera-PRO in D:/Andrey/Projects/Altera/DECA_DDR/DDR3C_sim/aldec directory.
asmi has been singing the virtues of Xilinx for months now and if he's happy to help out where he can, perhaps it's not such a bad idea. Naturally, there'd be a huge learning curve for me with the tool chain etc, but maybe it's time to address that elephant in the room?
/*
* GPU_GEO_tb.sv, for ModelSim and ***NEW Active-HDL.
*
* Features control from a source ascii text file script,
* and a 256 color .BMP picture file generator.
* Tested on free Altera ModelSim 10 & 20. Built in parameter
* (USE_ALTERA_IP) when disabled prevents the use of any Altera specific IP functions.
*
* Written by Brian Guralnick.
*
* v 0.6.001 Feb 01, 2021
*
* To setup simulation, Start Modelsim, The goto 'File - Change Directory' and select this files directory.
* Then in the transcript, type:
* do setup_ms.do
* (or if you want to enable the Altera megafunction IP, LPM_MULT & SCFIFO)
* do setup_altera.do
*
* To change the 'TB_COMMAND_SCRIPT_FILE' source script file string and re-run the simulation, type:
*
* do test_8bitfont.do
* do test_45deg.do
* do test_art.do
* do test_blitter.do
* do test_blitter_hires.do
* do test_vwait.do
*
*
*****************************************************************************
* For Active-HDL (Comes with Lattice Diamond FPGA developement enviroment.)
*****************************************************************************
*
* Go to 'File - New / Design'
* Create an empty design.
* Choose Verilog for HDL language, ignore 'Target Technology'.
* Type in 'GPU_GEO_tb' for design name.
* Next/Finish.
*
* Unzip all the files directly into the 'src' directory inside the 'GPU_GEO_tb' folder.
* In the console, type:
*
* do setup_active-hdl.do
*
* *** The result 'xxxx.bmp' and 'GEO_tb_command_results.txt' files generated by
* the simulation will be located in the main 'GPU_GEO_tb' folder.
*
* Active-HDL does not support the changing of a string in a .sv file,
* so to run the different tb ascii script demos, you need to copy the:
*
* GEO_tb_art.txt
* GEO_tb_Blitter.txt
* GEO_tb_Blitter_hires.txt
* GEO_tb_45deg_zilog.txt
* GEO_tb_8bit_font.txt
* GEO_tb_vwait.txt
*
* over the 'GEO_tb_command_list.txt' file, then do a restart & run simulation.
*
*/
Maker Model LEs Embedded memory I/Os Package Price
Xilinx XC7S25-1CSGA225C 23,360 1,620kbit 150 CSBGA-225 £24.23
Lattice LFE5U-45F-6BG256C 44,000 1,944kbit 197 CABGA-256 £12.09
Lattice LFE5U-45F-6BG256C 44,000 1,944kbit 197 CABGA-256 £12.09No, No, No, what is the price of the LFE5U-85F-6BG381C, 84,000 & 3,744kbit, 205 IOs.
Don't you want 1080p full motion MJPEG200 video playback & a full 3D accelerator?
BTW, XC7A35T-1FTG256I would have been a bit larger.
In other news, the DECA boards arrived just now. Can confirm there is no camera module in the box, just the board, couple of USB cables, Ethernet cable and power supply.
Ok, then see if the 'LFE5U-45F-6BG381C' exists. It should be pin-pin compatible with the -85F. It only appears to be missing 2 IOs in total.
XC7A35T-1FTG256I"I" in the end stands for industrial temps, it's more expensive than "C" variant.
Also - if you want cheap, you've got to go here Or here for 50T part. They've got a full assortment of Artix'es. Quality - unknown, price - cheap Should be good enough for soldering practice.
With Lattice part you will face the same issue you have with CV, namely lack of memory controller IP (or any other useful IPs for that matter). So why switching then? What benefits will Lattice part have over CV that will justify the switch, as well as possibly higher expense of having to go for 6 layer board due to 0.8 mm ball pitch? Currently there is a BIG jump in price between 4 layer boards and 6 layer ones, and JLCPCB's 6 layer stackup is no good for high-speed designs which require all 4 signal layers.
Nope, there are a lot of Lattice IPs including memory controllers for DDR/DDR2/DDR3. Problem is, those memory controllers are NOT free. (Available on the Lattice IP server.)
Has anyone used Efinix?
Take a look here: ' https://www.digikey.com/en/products/detail/efinix-inc/T85F484C3/11591358 '
However, It's like I cannot find the software dev tool download or complete documentation other than some video walk through, available ICs and dev boards.