I'm curious, did you verify that the IO are producing 3.0-3.3v out. If they are 2.5v out, you may need to lower the 3.3v voltage regulator on your PCB just in case.
My DDR3 controller is now available here:
https://www.eevblog.com/forum/fpga/brianhg_ddr3_controller-open-source-ddr3-controller/msg3606415/#msg3606415
assign Z80_WR_data[7] = data_en ? Z80_RD_data[7] : 1'bz;
assign Z80_WR_data[6] = data_en ? Z80_RD_data[6] : 1'bz;
assign Z80_WR_data[5] = data_en ? Z80_RD_data[5] : 1'bz;
assign Z80_WR_data[4] = data_en ? Z80_RD_data[4] : 1'bz;
assign Z80_WR_data[3] = data_en ? Z80_RD_data[3] : 1'bz;
assign Z80_WR_data[2] = data_en ? Z80_RD_data[2] : 1'bz;
assign Z80_WR_data[1] = data_en ? Z80_RD_data[1] : 1'bz;
assign Z80_WR_data[0] = data_en ? Z80_RD_data[0] : 1'bz;
EDIT: I'm just wondering if this bit of HDL could be the cause of the problem? Lines 305-312 in GPU.sv:Code: [Select]assign Z80_WR_data[7] = data_en ? Z80_RD_data[7] : 1'bz;
assign Z80_WR_data[6] = data_en ? Z80_RD_data[6] : 1'bz;
assign Z80_WR_data[5] = data_en ? Z80_RD_data[5] : 1'bz;
assign Z80_WR_data[4] = data_en ? Z80_RD_data[4] : 1'bz;
assign Z80_WR_data[3] = data_en ? Z80_RD_data[3] : 1'bz;
assign Z80_WR_data[2] = data_en ? Z80_RD_data[2] : 1'bz;
assign Z80_WR_data[1] = data_en ? Z80_RD_data[1] : 1'bz;
assign Z80_WR_data[0] = data_en ? Z80_RD_data[0] : 1'bz;
I'm just trying to work out exactly what's going on here to ascertain if this is the cause of the problem. Would certainly explain the 0xFF's being written to GPU RAM if there's an issue with data_en...
assign Z80_data[7] = data_en ? Z80_RD_data[7] : 1'bz;
assign Z80_data[6] = data_en ? Z80_RD_data[6] : 1'bz;
assign Z80_data[5] = data_en ? Z80_RD_data[5] : 1'bz;
assign Z80_data[4] = data_en ? Z80_RD_data[4] : 1'bz;
assign Z80_data[3] = data_en ? Z80_RD_data[3] : 1'bz;
assign Z80_data[2] = data_en ? Z80_RD_data[2] : 1'bz;
assign Z80_data[1] = data_en ? Z80_RD_data[1] : 1'bz;
assign Z80_data[0] = data_en ? Z80_RD_data[0] : 1'bz;
assign Z80_data = data_en ? Z80_RD_data : 8'bzzzzzzzz;
assign Z80_data = Z80_WR_data;
.Z80_wData(Z80_WR_data),
to:.Z80_wData(Z80_data),
This ties the Z80_data pins directly to your 'Z80_bridge_v2.sv' Z80 data input.Or, make your life easier:Code: [Select]assign Z80_data = data_en ? Z80_RD_data : 8'bzzzzzzzz;
And for the other direction,
However, you will need to kill line 684:Code: [Select]assign Z80_data = Z80_WR_data;
assign Z80_data = data_en ? Z80_RD_data : Z80_WR_data;
No, Z80 data pins must be set to a value, or HI-z so that those pins become an input.
The 'Z80_data[ x ]' are the IO pins. Reading this wire will always tell you the number whether it is an input of output.
This is why this one is tied to the read data in on the Z80 bridge.
Now, when you say 'Z80_data[ x ]' = [something], if that something isn't a 'z', it becomes an output.
So my code changes I recommended are correct.
Quartus made the booboo of making the output pins = to the assigned 'Z80_WR_data[ x ]' which was correct. But, there was no way to reverse send the data from the Z80 IO pins when set to 'z' back into the bridge unless the original line '684' was a bi-directional assign. If that assign is bi-directional, then there was nothing wrong with the original code and we need to look for the error elsewhere.
assign Z80_WR_data[7] = data_en ? Z80_RD_data[7] : 1'bz;
assign Z80_WR_data[6] = data_en ? Z80_RD_data[6] : 1'bz;
assign Z80_WR_data[5] = data_en ? Z80_RD_data[5] : 1'bz;
assign Z80_WR_data[4] = data_en ? Z80_RD_data[4] : 1'bz;
assign Z80_WR_data[3] = data_en ? Z80_RD_data[3] : 1'bz;
assign Z80_WR_data[2] = data_en ? Z80_RD_data[2] : 1'bz;
assign Z80_WR_data[1] = data_en ? Z80_RD_data[1] : 1'bz;
assign Z80_WR_data[0] = data_en ? Z80_RD_data[0] : 1'bz;
assign Z80_data = data_en ? Z80_RD_data : 8'bzzzzzzzz;
assign Z80_data = Z80_WR_data;
.Z80_wData(Z80_data),
Question: are you able to write valid changes to the control registers, IE screen position offset, zoom size. These are logic registers and are not part of the core memory. Do the settings take effect properly, yet read 'FF'?
Does the RS232 debugger work?
Can you read and write valid data there?
This will at least tell you the core ram is receiving and writing valid data internally.
Look at my DDR3 1080p output demo to see which IO drive the IC.
Look at my DDR3 1080p output demo to see which IO drive the IC.
Did you post the full project for that? I've only seen the .sof files?
Uhh, did you download my DDR3 project on my DDR3 thread.
There are full projects there, 4 of them + 2 additional source directories.
My instructions tell you which folders you can open in Quartus as a project.
Then go to the top file in the project and look.
Does your Z80 system have a clock/timing chip somewhere on it?
IE, can you test/time the speed of your reads?
This way, if we artificially enter a read delay with wait, can you tell is the performance slows down.
What I am thinking is during read cycle, add a timer/counter to delay placing the correct data on the Z80 output bus holding the wait and see if you can still read correct data.