-
-
Kleinstein - thanks looking at the schematic. The circuit is indeed quite complicated, but I did not see any obvious places to simplify it while maintaining the functionality. For example, a simpler ADC driver would be nice, but this one should make it possible to implement CDS to zero the ADC/driver offset and keep the NSD flat at low frequencies. Similarly, there are a number of level shifts using difference amplifiers, but I felt that would be the easiest way to implement the gate drive functionality I wanted, and the overall current draw is <2 mA, mostly from quiescent current of the op amps. If you see any obvious places for simplification, let me know.
The CD4051s should be TMUX4051, but I did not change the symbol names (this is necessary for 1.8V logic compatibility). They seemed like they would be fine from a resistance standpoint with 5V relays, but I looked at the maximum ratings, and they probably won't cut it. That block was a bit of an afterthought, and I now realize it would have destroyed itself. I will probably change it to something similar to what I used in the proof of concept version where I used a TMUX1134 (hopefully with a cheaper switch), but I am open to suggestions.
My target for bias current is +/-5 pA at 25 C, but I will settle for 10pA. The TLV1822 has a typical spec of 150 fA, so I don't think two of them should be an issue. You are right that Q17 and Q18 should not be necessary given the 10k resistor to limit current there, so I will probably delete them. I would like the inputs to be able to withstand at least 10V continuous, and I haven't decided what I want to do to ensure this. The window comparator is too slow to be used for transient protection, even if it is driving a FET switch. The absolute max Vgs and Vds for the PE4140 are 4.2V and 3.3V respectively, so it is definitely the most likely failure point. Perhaps it would be best to use back to back MOSFETs in series with IN+ driven by the comparator as well as bootstrapped diodes for transient protection. I looked at some fault protected IC switches for this purpose briefly, but none really fit the bill for pA leakage and low resistance. This is a tough case for robust input protection given the requirement for low source impedance, and I am open to better ideas.
-
#51 Reply
Posted by
Kleinstein
on 08 Jan, 2024 20:22
-
The input protection is indeed a tricky part, especially with the series element to limit the current. One option may be a PTC and than rather robust clamping diodes (e.g. more 1N4007 and not only BAV199). It is still the question if the PTC may cause some thermal EMF error. At least the one I tested (relatively high resistance THT part) was OK with hardly any extra thermal EMF error.
Another option is back ot back FETs (depl. mode or MOSFETs with OV OK as voltage source - here one needs to be rather careful with temperature gradients as these can cause thermal EMF errors. In my DMM circuit I get an offset of some 500 nV from the protection, which would not be good for a nV meter. For only a low voltage one may get away with a pair (maybe 2 in parallel) low R JFETs as current limit. With no active power consumption one may be able to keep thermal gradients small.
For the circuit one may get away with a simpler ADC driver, without the extra buffers. It is still possible to just start with a bridge instead of the buffers and keep them as an option. It may be enough to limit the supply to the driver instead
For the demodulator part one may get away with a simpler switch, maybe 4053 type that could be directly controlled.
-
-
I did think about depletion mode MOSFETs, but the ones I am aware of (like the LND150) have excessive rdsON. The PTCs I am aware of are ms time-scale devices, which is something I could cover with the relay. I could couple a switch like the TMUX1121 (or a single SPST) with the window comparator to be able to turn off the input within around 600 ns and clamp any transient in that time to the supply rails for the switch and open the relays at the same time. Presumably a bootstrapped diode clamp of some description could survive such a transient for the ~1 ms it would take to open the relay. Limiting the rise time of the signal with a ferrite bead and a capacitor is a possibility, but making rise times >>1 us is probably not feasible this way. If anyone is aware of a low rds on latch-up proof switch, that would probably be ideal for limiting input current between 1 us and 1 ms.
I was going to use an integrated switch for the demodulator originally, but in simulations, even low charge injection ones (like the ADG1219) led to charge being injected back to the input as well as some ringing. With the +/-1 V gate drive signals I'd be using for the demodulator, the injected charge is only about 4 fC with no deadtime or about 5.5 fC with 100 ns. Given that, I thought it would be easier to just duplicate a block I had already used for the modulator.
It may be possible to skip the drivers and use the THP210. I may put in some jumper footprints to try that. I see a 0.01% settling time of 1.2 us for the THP210 with a 10V jump, so with a much smaller load transient and ~1.7 us to settle that might work.
-
#53 Reply
Posted by
Andreas
on 09 Jan, 2024 07:51
-
I will probably change it to something similar to what I used in the proof of concept version where I used a TMUX1134 (hopefully with a cheaper switch), but I am open to suggestions.
Hmm,
In your design the Inductivity is switched off hard. So I am missing the free wheeling diodes to protect the MUX.
I am usually using (via capacitor) a (high current) port pin of a 5V controller.
E.g. a ATMEGA168P which has around 25-30 Ohms to drive a coil (178 Ohms) of a TQ2SA_L2 relay.
No hard switch off by the capacitor. -> no free wheeling diodes needed.
The downside is that after a switching I have to wait some 100 ms until the capacitor is fully loaded/discharged.
On initialisation of the controller I use the internall pull up resitors to charge the capacitor slowly.
A reconfiguration of the PORT pin to output + LOW level gives a defined state for the relay.
with best regards
Andreas
-
#54 Reply
Posted by
Kleinstein
on 09 Jan, 2024 11:05
-
For the relay swiching I use drivers like 74AC540 and the 5 V coil between 2 such outputs. 74HC with a 6 V supply may be an option too. It is not ideal with the drive strength, but is just enough for the low power latiching relays (EE2 or FTR1). When uses as a chain and switching 1 relay at a time it only needs N+1 outputs. The advantage over the capacitor version is less chance for accidently switching on power up / down.
For the protection there are depletion FETs with lower resistance. E.g. BSS159 or BSP135. JFETs like 2SK2145, would be an option too - if needed 2 or 3 in parallel, which is not that bad with the relatively small cases. Ideally one wants some with a relatively low threshold to get a reasonable low current with not too much resistance.
If the charge injection is a problem, the same / similar switch for the demodulator could be OK, maybe with a simpler (fixed or manual trimmer) setting for the voltages.
-
-
Andreas - The relay idea I used was bad. It was one of those end of the day/trying to wrap it up things. The digital section here is 1.8V, so really any relay drive is going to require some sort of level shift. I could use the capacitor thing with an SPDT switch, which I have done before, but the ~100ms charge time here could be a deal breaker if switching off a relay within ~1ms is required to keep whatever protection method I use within its SOA. Honestly, my favorite way is using dual LVC gates. At 4.5V, they have sufficient drive to trigger a 3V coil for an Omron G6KU, though a Panasonic 3.6V TXS2A might be a better choice with something like a 74LVC4225A.
Kleinstein - I will look into using the FETs you mentioned. The BSS159 has reasonably low Rds with Vgs = 0V at 3.5R, so putting those back to back would only increase en by about 5% from the case of having the PE4140 as the only source of input resistance, which is acceptable. I am going to start working on component placement for other blocks and circle back to this, but I'll post a revised pdf for the schematic of the input switching and protection when I get there.
-
#56 Reply
Posted by
Andreas
on 09 Jan, 2024 19:11
-
if switching off a relay within ~1ms is required to keep whatever protection method I use within its SOA.
Hello,
this was only a suggestion from my side to keep the effort low.
For the switchoff duration I would calculate minimum 2-4 ms for the typical signal relays.
For the TQ2SA_L2 it needs ~2,2 ms until the anchor movement is done with full reverse polarity during switch off
(without free wheeling diodes).
with free wheeling diodes (I hope you do not rely on the internal diodes of the driver IC) it will last longer.
Datasheet specs are typical 4 ms. (without free wheeling diodes).
with best regards
Andreas
-
#57 Reply
Posted by
Kleinstein
on 09 Jan, 2024 19:23
-
A classical relay is a bit slow for the protection without resistors to limit the current. It can be a secondary thing to prevent thermal problems with the faster protection and than a few ms more should not be that bad.
A reed relay may be a littel faster, but these are non latching and thus permanent heat sources.
For limiting the very fast transients one can use an inductor of a few mH - this is used e.g. in the HP34420 and other nV meters.
-
-
Andreas - I do appreciate the suggestion and the info on release time. I rigged up a little jig to see how consistent the release time was with the setup I had mentioned, in this case using a 74LVC2G17 with the outputs attached to a TXS2-L-4.5V-1 I had on hand. The one input is attached to Vcc and the common is attached to ground via 100R (Yes, this is probably killing the relay contacts). With this setup, I am consistently getting 1.86-1.88 ms at 5.4V (which I would probably use as I already have that rail available in the design). At Vcc=5V, the release time increases to 1.98-2.00 ms, which is consistent with your data. It has been clicking back and forth at 20 Hz for about 40 minutes at this point, so there don't seem to be any problems with flyback voltages during the brief time between states that the gate becomes high impedance. I attached a capture of the switching trace (at the relay output) and one of the turnoff, showing that the output of the gate does not get driven significantly below 0V. By the way, this continues to work down to 2.5V without any missed transitions, with a release time of about 5.1 ms. The cutoff seems to be around 2.3V.
Kleinstein - You are right that this is too slow to use for protection, so I think I will probably go with a depletion MOSFET pair back to back to limit current. It may be possible to put an inductor on the input to limit rise times with some RC damping on the input, and I will probably do this (or use a FB) with the value based on how quickly I can turn off the FETs.
-
-
I have decided on an input protection method and completed the schematics for the power supply, so I have attached some updated schematics.
The input protection uses a 75V GDT (no MOV because the input voltage range is very small) and CPC3902 depletion mode MOSFETs on both inputs. The CPC3902 is rated for 250V and has an RDSon of 2.5 Ohms at zero bias. When IN+ goes above 0.7 V, the FET on IN+ is turned off by a comparator (propagation delay is about 300 ns). When IN+ goes below -0.7 V, the FET on IN- is turned off. The hysteresis on the comparator for undervoltages is kind of weird, but I found in simulation I needed the turn on threshold to be very low to avoid oscillations. I will probably need to add some more inductance to IN+ to limit current for fast rising signals, but I will figure that out as I get into layout.
The power supply uses two buck LT8608S converters to generate 8.5V and 2V rails. The 2V output is fed into a Cuk converter using an LT8365 that is powered with the 8.5V rail to generate -3.4V. The Cuk was somewhat painful to compensate in simulations, but it seems to be reasonably stable. Also, I couldn't find any loosely coupled inductors that seemed suitable, so I just used a normal coupled inductor and added a single inductor to the output. I was having problems with coupling factors above about 0.95 in simulations. There won't be large load spikes on the negative rail, so I don't think the long response time of the compensation network will be too problematic. I had wanted to use a switched cap inverter for this, but I couldn't find any that seemed a really good fit for the application, especially because I didn't want to have to power it with the +5V4 LDO. The power supply is a separate module because I wanted to keep as much power dissipation off the board as possible and I wanted to be able to try something else if this ended up negatively impacting noise. By the way, I left all the oscillators free running rather than trying to sync them to a clock on the board. I am curious about opinions on whether this will be problematic.
-
#60 Reply
Posted by
Kleinstein
on 11 Jan, 2024 20:35
-
I don't think the protection with Q20,Q21 is really optional. It schould be the main way of clamping. For simplicity I would prefer a BAV199 there (should also fit on one of the footprints of a MMBF4117).
The input protection with the FETs on different sides is a bit unusual, but it could still work.
I think some of the capacitors (e.g. C119, C1120) in the ADC drivers are a bit large and would slow it down a bit much.
With the gain at the ADC driver, the input protection via the switches may engage a bit late. So maybe have the option for lifted levels (e.g. 3 more resistors) at U32.
-
-
Thanks for the comments. You are probably right with the settling time of the ADC driver, and I may reduce the caps to 1.5 nF. It takes about 120 us to settle to 1 ppm with the current values from a full-scale step, which could probably be better. My plan for using CDS for the driver was to have that clocked at 1/2 the speed of the modulator, so it would share that settling time with the input stage settling. From ADIs simulator, it seems like the 68R/2.7nF combo for the ADC input should be settled to <0.1 ppm at 500 kSPS as far as charge kickback goes.
Good idea on popping a few resistors in to shift the levels on U32 in a few tenths of a volt.
My goal with the clamp was to have the bootstrapped BAV199 clamp the voltage at about +/-3V, but that is playing pretty close to the line for the PE4140. A BAV199 in the place of the 4117s would be more robust, so I think you are right about making that switch. I'll keep it as such because I can just sub in a BAV199 for one of the FETs as you mentioned. I realize the FETs on both inputs is somewhat odd, but I realized that with N-channel FETs being driven by the voltages available on the board, there would be no way of turning off a FET on the positive input for a large negative overrange. This wouldn't be an issue with JFETs, but I thought it would be better to have the series current limiters survive until sparkover on GD1 at 75V, and options for 75V JFETs are very limited. I kind of like this more than back to back FETs for a NVM because I can use the symmetry to cancel out thermal EMFs, presuming I can accurately guess the direction of the thermal gradients.
-
#62 Reply
Posted by
Kleinstein
on 12 Jan, 2024 06:06
-
The settling at the ADC driver is not so much the 68 ohm and 2.7 nF, but the presumibly 3 K and 2.7 nF at the x3 gain part. Anyway changing the values is a thing a think about later.
For testing it could be good to have an option to have an alternate input path to the ADC - maybe even via U34C.
In the circuit I don't see many test points.
For some of the parts that see higher frequency operation (e.g. U38 as the final ADC drivers and maybe the ADC) it may help to have additional resistance (e.g. 5-10 ohm) or ferrites in the supply paths (before the decoupling caps). This can keep the supply cleaner.
-
-
Points well taken. I have plenty of room on a 150x100 mm board, so I am adding test points as I go. Note that the gain of the composite diff amp is 2 (Rg = 700R, Rf = 1k4). I like the idea of being able to feed a signal to the ADC directly using the unused section of the TMUX4053. I may also add a footprint for an ADR1399 daughterboard to have the option of a higher quality reference.
I am making pretty good time on layout, but it is not easy. I have moved the components that dissipate the most heat out from the RF shields that I am using as thermal baffles and put in cutouts to isolate the sensitive parts from external thermal gradients as much as possible.
-
-
A quick status update. I have finished laying out the board(s) for rev B of the NVM and written a decent chunk of the setup code. I attached 3-d renders of the top and bottom of the boards. On the top, the signals start in the upper-lefthand corner and move down and right. The MCU is the LQFP-64 in the lower right corner. I was glad to have done some of the coding before finalizing the board design, because I realized my original timer scheme was not going to be optimal for what I needed to do. I have attached a quick timing diagram of what an autozero cycle would look like, but it does not include all the outputs. I will beef this diagram up at some point to make it more understandable. There are two synched timers that control the PWM signals for the (de)modulators with the same period, one with double the period for CDS for the ADC, and one with half the period (i.e. synched to the phases of the modulator timers) where the output compare triggers the timer that pulses the CNV pin on the AD4032. To make this easiest, the CNV pin needs to be attached to TIM1 or TIM8 on an STM32 because they have a repetition counter. The timer that triggers the CNV timer allows one to adjust the settling time of the input before starting conversions with the ADC. Also, the modulator and demodulator timers needed to be 32-bit timers to give fine control of the switching deadtime while allowing (essentially) arbitrarily long autozero cycles.
The BUSY pin is connected to an external interrupt pin that triggers a read of the output data shift register of the ADC. I noted in a previous project that with an STM32F446 at 180 MHz, I could get a time of 160 ns from the falling edge of the BUSY signal to the falling edge of the NCS signal. With the QUADSPI bus clocked at 90 MHz in that case, I could retrieve the data from a previous conversion on four lanes before the next pulse of the CNV pin at 2 MHz with margin for the 19.6 ns quiet zone (Zone 1 transfer, see AD4030-24 datasheet p. 29). At 500 kSPS, that window is ~6x longer, so I should be able to run the MCU at 48 MHz, assuming things scale linearly. I expect it will be a bit better than that because the U5 uses the Cortex M33 instead of the M4. Obviously, none of this is possible with STM's HAL. I will post all this to Github tonight or tomorrow and share a link to the repository.
While I was laying out the board, I realized that my comparator-driven input protection scheme would not easily be made to work for powered-off input protection, so I changed it to what I think to generally be a better scheme. It is more or less a depletion mode FET current limiter. For the positive input, the gate of Q2 is connected to the source via R79 and Q13 (the latter as a low-leakage diode). With typical specs for the CPC3902, this puts the current limiting at 10 mA. With maximum Vgs_off, it would be ~15 mA. D13 and D12 are low capacitance RF Schottky diodes so that the input is not burdened with the large Ciss of two CPC3902s in parallel. The FBs and dampers (R1 & C1, R81 & C47, and R76 & C48) are there to deal with spikes from fast rising signals coming through the Coss of the FETs. In simulation, this kept the voltage between the nodes K2_IN+ and K2_IN- at <3V even with 100V spikes with a rise time of 1 ns. The maximum current through the FETs allows a constant voltage of 100V over either Q2 or Q1 while remaining safely under their maximum power dissipation of 1.8W. With typical values for Rds_on, the source impedance seen by the input chopper is ~5 Ohms in series with 1 uH. In simulations, the phase margin of the input chopper is about 80 degrees with the equivalent input impedance of this protection block in place.
-
#65 Reply
Posted by
Kleinstein
on 30 Jan, 2024 19:01
-
It is an interesting way to make the protection. Looks like it may work, as long as the input is OP with the voltage needed to turn of the depl. FETs. The maximul current may well be lower than 10 mA, as there is also quite some voltage drop at the diode / diode used JFET. It can be a nice version with low series impedance, but it is somewhat limited in the voltage.
-
-
I am not too concerned about the current limit being less than 10 mA. It is actually not that difficult to change this to work with arbitrary voltages. For positive input protection, for example, you can put a zener in between R78 and K2_IN+ and bootstrap the node between the zener and R78 with some moderate impedance. The gate for Q2 would be connected to this node as well, via R80 and D12. Such a scheme should limit the input voltage to ~V_zener + 2 V with minimal leakage and additional capacitance. You would probably want the bootstrap to rail out around the zener voltage.
By the way, I have created the github repository. Here's the link:
https://github.com/curtisseizert/Nanovoltmeter
-
-
I had to put things on hold a bit while I did some work on my house, including replacing the old knob and tube wiring. My reflow oven had been working on a 15A branch that was wired with ~120 year old 14 gauge Al wire, where neutral was regularly 5-7 VRMS off ground without it on. Also, I had grounded my instruments through the shield of some 75 Ohm coax that plugged into my UPS. It was sketchy.
Anyways, I have assembled two NVM main boards, one using an LTC6655, and one using an ADR1399. By the way, I switched the heater leads in the pinout for the ADR1399 on the schematic (and boards I had made), so I will post a revision on Github. There are a lot of components on this board (about 470 with the ADR1399, somewhat fewer with the LTC6655), and it took quite a while to populate the boards. This is about as complex a board as I would want to hand assemble. Apparently when I was sourcing components, I was too cheap to get enough of the BMF gain setting resistors for two boards, so those are not populated on the assembly I have shown. There is still some more code to write, so it will be a bit longer before I can power it up and test it. Also, I did select the JFE2140s I used in this case, and I was able to get the average Vos down below 15 uV in both cases, so I may be able to reduce the gain on the Vos correction loop more, but I will try it out before I made that modification.
I also made a separate board where I just populated the input protection circuitry to be able to abuse it, so we will see how that works.
-
-
A quick status update: I haven't finished writing code that works quite yet. As I may have previously mentioned, I am not using STM's HAL and am going for direct register-level coding here because I found in some previous work that there was too much overhead in STM's drivers to meet strict timing requirements for completing transfers from the AD4030-24 on the QSPI bus at 2 MSPS. That was done with an STM32F446 (Cortex M4), and this uses an STM32U575 (Cortex M33), and there are some differences in how things are set up. Hopefully I can get something working over the weekend.
The PSU daughterboard positive rails work well, but it will require a revision for the Cuk. I like the LT8608S buck converters for efficiency and noise. The 8.5V output is about 83% efficient at 26 mA current draw, which is the minimum required to get it from burst mode to pulse skipping mode. Noise on that rail is a few mV p-p out to 100 MHz. If I float the SYNC pin, it should stay in pulse skipping mode, which is less noisy. I still need to test the efficiency of the 2V output, since it draws a lot more current; it feeds both the 2V rail and the Cuk converter that is used to make the -3V3 rail (in order to keep the duty cycle for the Cuk in a reasonable range). A revision is required to correct the pinout for the coupled inductor in the Cuk and have everything fit under the shield. I tested it with a couple transformers I wound for the purpose, but I'd like everything to be clean to keep radiated emissions to a minimum. I also added some snubbers to the switching nodes of the buck converters in the revision because they are operating in DCM, though the output noise is good without them.
Both the ADR1399 and LTC6655 versions of the board power up successfully now, but I had to fix some schematic issues with the ADR1399 block. I have attached the corrected schematic. As drawn, it will not be able to maintain current regulation at very low dropout conditions for ADR1399 voltages near the upper end of the range, so that will be something to consider for a future revision of the main board. With an MMBF108, R154 = 25R, and R70=3.3M, this should keep the reference current >3 mA for the whole range of possible reference voltages, with a minimum dropout voltage of 0.2V. It may also be preferable to omit C156 for better PSRR. I haven't seen this sort of topology used in this application, but perhaps there are instances I am not aware of. The block surrounding U42B is just for ground current cancellation.
The input protection circuitry works well for slowly rising overvoltages applied to the inputs, which I have tested up to 60V. However, it seems to ring with quickly rising voltages, so the input chopper would be subjected to +/-10V for about 20 ns if one plugged in 60V, at least with the current values for resistors, capacitors, and ferrites. The voltage was clamped at 2.3-2.4 V for each rail, and the current when the voltage exceeds this was 6.5-7 mA (it is slightly different for each rail). If I short the inputs after the protection circuitry, the DC resistance is about 4.4R. The capacitance of the input section is 210 pF at 1 kHz (with 0.2V excitation), which is only 30 pF more than the total value of the snubbers. Of course, there is a fair bit more capacitance from Cgs of the depletion mode FETs, but that is in series with 1M. I am going to keep playing around to see if I can improve the performance with quickly rising overvoltages with some different component values, but I am happy with what I have seen outside of that.
-
#69 Reply
Posted by
miro123
on 23 Feb, 2024 22:18
-
Thanks for the update.
There are a lot of innovation going on your project. From analogue technique to power eletronics and then the digital bleeding edge technologies. Are you using STM32U5 DMA Low-power background autonomous mode? Are you using STM32U585 SMPS or just use external dc-dc- cuk's
Send me a PM if you need help with STM U585 setting
-
#70 Reply
Posted by
Andreas
on 24 Feb, 2024 05:53
-
-
#71 Reply
Posted by
Kleinstein
on 24 Feb, 2024 08:19
-
The low side of the ADR1399 reference looks a bit odd. There is the rather low resistor to "measure" the current, but essentially all of the current would still come via the transistor.
I have not seen this part in the initial circuit and it is now likely too late for a larger change. A more logical solulution here might have been to have the 7 V reference split as +5 V and -2 V. So that the high side could directly be at the 5 V ref. out level and the -2 V level could be controlled be the "gain" stage to get -2/5 of the high side. So with no direct ground link for the refrence. One would get a little more headroom to control the current from an auxiliary level of some +7 V.
For the protection against fast transients some series inductance could help. It would still let some current through, but the current is at least reduced and as a side effect one gets some EMI filtering.
-
-
Thanks for the update.
There are a lot of innovation going on your project. From analogue technique to power eletronics and then the digital bleeding edge technologies. Are you using STM32U5 DMA Low-power background autonomous mode? Are you using STM32U585 SMPS or just use external dc-dc- cuk's
Send me a PM if you need help with STM U585 setting
Thank you. I may need to take you up on that. I actually mislabeled the schematic and am using the STM32U575RIT (not Q), which just uses an LDO for the core voltage. Simply using a low power MCU at a low voltage helps a lot with power consumption (and, importantly, fed with a buck regulator). Once I get some minimal code going, I may work on implementing some of the fancier low power modes. I have attached the revised schematic for the PSU daughterboard. The 2V0 rail feeds TPS7A20s to make the two 1V8 rails. The Cuk is only for the negative rail as I have found they are often difficult to compensate at very low current draw.
I am going through the debugging process to make sure the various peripherals are up and running on a separate board with just the MCU and associated components. I am really still in the stages of learning as I go with coding some of this stuff, and the way it is currently set up is fairly basic with a handful of interrupts and GPDMA for the octospi bus that receives data from the AD4032. I am not aware of any good bare metal code examples for this series that goes beyond blinking a LED, which I can handle fine on my own. Right now I have all the timers working as planned, which was the most complex part of planning out the code so far. There are separate 32 bit GP timers for the modulator, the demodulator, the ADC CDS routine, and the settling delay between switching phases before beginning ADC conversions. The CNV pin is pulsed in one shot mode using one of the advanced timers (TIM8) for the repetition counter, and the falling edge of the BUSY signal on EXTI0 triggers the data read. With all the peripherals running and SYSCLK at 48 MHz, the oscillators and MCU pull about 10 mA, so that is 20 mW, which I don't think will be a big problem as it is a small portion of the overall power consumption.
I am interested to see if the response time to an external interrupt is better for the M33 than it is for the M4. With the F446 at 180 MHz, the best I could do was 160 ns between the falling edge of BUSY from the ADC and the falling edge of NCS from the MCU, though in that case I did not have hardware control of NCS, so it took a couple cycles to write the appropriate GPIO register. There is probably a better way to do this, but triggering ADC data reads with the falling edge of BUSY is probably the easiest way to code it. At 2MSPS with the Q- or OSCTOSPI clock at 90 MHz and 4 lanes, you need to be at or below 100 ns to get within the available window of 198 ns with a bit of margin. At 500 kSPS, I have a much more leisurely 1.2 us, so this naive way of structuring the transfer will probably work.
Hello,
where comes the heater supply from?
with 10V (+7.5 / -2.5) you are in a area where the PSRR is worse than 1 ppm/V.
Ideal would be something around 25-26 V for the heater.
https://www.eevblog.com/forum/metrology/adr1399-reference/msg4503037/#msg4503037
with best regards
Andreas
I was not aware of that rather poor heater PSRR. As I currently have it, the heater gets the battery voltage for the positive supply and the Cuk output (-3V3) for the negative. In theory that would be 20V at full charge to about 15V with the cell voltages at their cutoff of 2.9V. Obviously, if that 1 ppm/V is a general phenomenon, this would be a big issue, but I could address it with another converter on the power supply at the expense of no longer being able to monitor the battery voltage with the MCU ADC. I don't mind this too much since I will already be doing a revision of the PSU. I will check the PSRR with my setup and report back. Thank you for bringing this effect to my attention.
The low side of the ADR1399 reference looks a bit odd. There is the rather low resistor to "measure" the current, but essentially all of the current would still come via the transistor.
I have not seen this part in the initial circuit and it is now likely too late for a larger change. A more logical solulution here might have been to have the 7 V reference split as +5 V and -2 V. So that the high side could directly be at the 5 V ref. out level and the -2 V level could be controlled be the "gain" stage to get -2/5 of the high side. So with no direct ground link for the refrence. One would get a little more headroom to control the current from an auxiliary level of some +7 V.
For the protection against fast transients some series inductance could help. It would still let some current through, but the current is at least reduced and as a side effect one gets some EMI filtering.
Yeah, that probably would have been better. I have quite a bit of experience using that ground current cancellation technique in ADR1000 and LTZ1000-based reference modules for ensuring that the low sense voltage remains near power ground with potentially variable contact resistance on the header, and it works well for that purpose. With the OPA2205A, things usually settle out to a few tens of uA ground current. It is nice to have a low current sense resistor because it changes the cutoff frequency for op amp noise. With the values here it is only about 4 Hz. So it may not be ideal, but it does work, and you have to admit that the current source for the Zener is pretty cute.
I agree some series inductance would help. With all the beads in series, I think it should be around 2.4 uH right now, which is not much. I am wary of adding too much given my experiences with degrading the phase margin of composite amps with a large input capacitance, especially since the autozeroing with this is predicated on the discrete portion operating at very high gain (from simulations, it is about 70 dB), which means the loop gain is quite high even with a large divider in the feedback network. That said, I can experiment pretty easily by just adding ferrite beads to the input leads or adding turns to said ferrite beads. I was thinking about trying out Toshiba's Amobeads for this purpose along with more traditional cable ferrites.
-
#73 Reply
Posted by
miro123
on 24 Feb, 2024 23:54
-
I am going through the debugging process to make sure the various peripherals are up and running on a separate board with just the MCU and associated components. I am really still in the stages of learning as I go with coding some of this stuff, and the way it is currently set up is fairly basic with a handful of interrupts and GPDMA for the octospi bus that receives data from the AD4032. I am not aware of any good bare metal code examples for this series that goes beyond blinking a LED, which I can handle fine on my own. Right now I have all the timers working as planned, which was the most complex part of planning out the code so far. There are separate 32 bit GP timers for the modulator, the demodulator, the ADC CDS routine, and the settling delay between switching phases before beginning ADC conversions. The CNV pin is pulsed in one shot mode using one of the advanced timers (TIM8) for the repetition counter, and the falling edge of the BUSY signal on EXTI0 triggers the data read. With all the peripherals running and SYSCLK at 48 MHz, the oscillators and MCU pull about 10 mA, so that is 20 mW, which I don't think will be a big problem as it is a small portion of the overall power consumption.
I am interested to see if the response time to an external interrupt is better for the M33 than it is for the M4. With the F446 at 180 MHz, the best I could do was 160 ns between the falling edge of BUSY from the ADC and the falling edge of NCS from the MCU, though in that case I did not have hardware control of NCS, so it took a couple cycles to write the appropriate GPIO register. There is probably a better way to do this, but triggering ADC data reads with the falling edge of BUSY is probably the easiest way to code it. At 2MSPS with the Q- or OSCTOSPI clock at 90 MHz and 4 lanes, you need to be at or below 100 ns to get within the available window of 198 ns with a bit of margin. At 500 kSPS, I have a much more leisurely 1.2 us, so this naive way of structuring the transfer will probably work.
Few thinks comes in mind.
1. You can use the nucleo board for software debug and prototyping. HW design of those boards not good but they are perfcest for sw validation.
https://www.st.com/en/evaluation-tools/nucleo-u575zi-q.html2. Honestly I did not follow completly your design and requirements but few this pop up in my mind.
- using GPIO for time critical application is not the good way. Modern processors has many busses and bridges between. This allows nodes with different speed to communicate efficiently. The GPIO periphery is ot directly connected to CPU core as it was in old days - 8051/PIC and AVRs. Just for test try to togle one pin in one endless loop. You will see that frequency does not strongly depend on CPU core sped. More from global picture mostly from all bus speeds
- The main STM32 advatage is the periphery and interconnection between them. In general - all what we do in FPGA can be done with programming of periphery. Unfortunately the kerning curve is quite steep. Most variant have 2000+ pages URM pdf. + datasheet 100..200pages + App notes.
My advice is to use time compare-capture capability - reaction time there is in nsec range -
Interconnection between periphery happen via triggers and events. - I suspect your application requires
solution 1 - SPI ISR
- Timer CCR output start external ADC - ADC toggle STM Interrup Input - ISR hanle data
solution 2 - Poll spi for data
precondition - init spi + spi FIFO
- Timer CCR output generated start pulses using the same setting as solution1 - timer period is set to 2usec. - 500KHz
- Main loop pools for SPI data
Soluti0on 3 - Use DMA - the one that I preffer . Disadvantage requires deep dive in STM documentation or you can ask me to write some demo code using STM Cube and HAL
-
500Ksps - seem easy task. I have been running 100MHz QSPI to execute code from external SPI flash But EMC /radiated/ was terrible. Does ADC support LVDS outs?
-
-
It is difficult to fully explain what needs to happen in the code here, but the software NCS for QSPI was on an old project where I realized I needed to change pins. Anyways, nothing time critical on GPIOs here, and there are a lot of synchronized timers. Basically, the ADC is oversampling, so I am not even clocking out 500 kSPS as it does internal decimation. I am using OSRs in the range of 64 to 1024. With the 1.2 us window I have, I am almost certainly going to use the falling edge of BUSY from the ADC (connected to EXTI0) to trigger the read. Right now I use an ISR to do a blocking transfer over OCTOSPI using hardware NCS. It would be nice if I could trigger OCTOSPI to read the ADC data directly with EXTI0, but I haven't figured out how to do that yet. Because of the OSR, I actually cannot use a CC on TIM8, which handles timing for the conversion cycle, without checking the state of the BUSY signal.
I do actually have things up and running to some degree now. The MCU DAC and the AD5686 are working and providing the switching levels. There was an oscillation due to Q19 sourcing more current on the Vcm node than the op amp driving it could sink, but I was able to take care of that by bending up the leads for the collectors and soldering in 10k resistors to Vcc. It is not performing as expected yet, but I will keep troubleshooting. It looks like the current draw at 500 kSPS (with the LTC6655) will be about 32 mA on the 8V5 rail (about the same on -3V3) and 18 mA on the 2V0 rail, but this could come down a bit when the loop is actually regulated.