To be honest I'm a bit confused by ST's new MCUs.
The STM32F103, STM32F207 and STM32F407 were classics that made pavement for a lot of the other MCU models. The F42x series added SDRAM and LCD support, the F446 had QuadSPI memory expansion, and then later the F7 and H7 models were introduced with Cortex-m7, more memory, SDMMC, etc. Some of these chips (in particular F7) had very similar peripherals to the F446 chips. Then ST has sort-of aa 2nd gen of MCUs in the H7 family that introduced a new memory controller e.g. OctoSPI, which follows up on quad SPI so you can utilize dual-bank FLASH and/or even HyperRAM. The U5 MCU also has this memory controller, and it's great if you want to run code from external memory. The QuadSPI FLASH controller can have a random read latency of up to 430ns on a L1 cache miss, which is an eternity (93 cycles @ 216MHz)
That's all great: but meanwhile, they were also able to maintain other useful peripherals of the F4 family. For example, the F4 family has USB OTG FS+Phy and OTG HS+ULPI, which can be useful for high bandwidth PC applications. The U575, G4 and H5 series seem to have left these peripherals out and only includes a "USB FS host and device" peripheral. So I wonder: why a step backwards?
All these chips are on a better level of speed/memory as the original F207/407 chip, so I don't see why these chips wouldn't be able to carry USB HS data. Maybe it's an IP licensing issue, maybe a low customer demand issue, but I find it confusing that they have omitted this peripheral for 3-ish new generations in a row. I do see they list USB HS on the newer U59x chips, which is great, but still makes me wonder why they fragment their U5 lineup with only USB FS on the U575.. If anything I'd make a guess it makes more sense to consolidate several variants to the same die design, so they can be sold from the same wafers.
Ah well, can't complain and probably will never know. I never viewed ST's MCU as especially focused on 1 area, such as industrial, which IMO is a key ingredient to their widespread adoption. I think that with their mainstream line-up listing "ALL" option boxes was a great strategy. E.g. I once tried to design with a Microchip/Atmel Cortex-m7 chip, and was purely shocked that a 300MHz 100QFP device would only have 2 SPI interfaces