Hi - can you comment on why you used an inverting op amp configuration? Typically you see electronic load circuits that use a non-inverting op amp configuration, so just wondering if there were any particular advantages to the non-inverting configuration (e.g., stability, easier to configure the summing node, etc.)?
Hey Jay your project is listed over on DP.
http://dangerousprototypes.com/2015/01/20/diy-dynamic-electronic-load/
Jay_Diddy_B,
Thanks a lot for putting in the effort to explain your analysis. It is by far the most clear explanation I've seen so far. It is the most useful explanation I have seen so far ...
Could you explain in a bit more details please how you read the last two charts of your post. Specifically, how do you determine if the circuit is stable.
If I read it right, the unity gain of the loop is at 30 kHz. But in both cases (before and after dampening is added) the phase shift seems to be pretty far away from 180.
Or do I read it wrong?
Thanks.
Hi,
I have zoomed in on the area that we are interested in. Here is the results without the damping network:
I have used arrows to indicate the phase margin and the gain margin. The phase margin is a very good 84 degrees. The gain margin is low, only 3dB.
If I add the damping network. I get the following result:
I have the same phase margin 84 degrees, but the gain margin has increased to a massive 52dB.
So why is this problem?
Both of these loops are stable. The issue is that part of the control loop, the transconductance of the MOSFET varies with the operating point. The gain increases as the current increases. If I modify my model to this:
Here I am stepping the load current from 0.5A to 5A. I get this result:
The high current result is unstable, the gain is 3dB when the phase angle is 0 degrees.
If I switch to the time domain. In this model I am ramping the load current from 0 - 5A:
I get this result:
You can see the control loop breaks into oscillation when the current is greater than 1.9A.
Note, that I had to add a little ripple, just 10mV, to disturb the control loop to get the oscillation to show up.
If I add the damping network I can sweep the current from 0-5A and there are no oscillation as predicted in the frequency domain. (There is nothing to see, so I have not included the results).
An alternative solution to the damping network, is to reduce the loop gain. If I increase the capacitor by factor 10, to 2200pF, I get this result:
This is a very stable system, but the limited bandwidth, would prevent the circuit being useful for transient load tests.
Regards,
Jay_Diddy_B
Hi Jay,
Do you have a PCB layout file or Gerbers you can post for this circuit?
Thanks,
Sam
W3OHM
... <snip>....
Features:
0-5A maximum continuous current
0-5A pulsed current at 330Hz
This model uses an IXYS generated model for the MOSFET, downloaded from the IXYS website. I am not sure about the small-signal accuracy of this model with low Vds.
A large MOSFET in this application does not require large GATE currents. Here is the gate current waveform:
Thanks a lot Jay ! Definitely this will be my nice project for the upcoming end of the year holidays.This model uses an IXYS generated model for the MOSFET, downloaded from the IXYS website. I am not sure about the small-signal accuracy of this model with low Vds.
What does this mean ?
What do I need to look at, especially low Vds as in testing low voltage power supply ?A large MOSFET in this application does not require large GATE currents. Here is the gate current waveform:
Is that because we don't need a really-really fast turn on/off ? Say at sub microsecond ?
I don't see anything in the model that accounts for the step in Crss. The value of Crss changes by a factor of 10.
Because of this step, the MOSFET behave differently at low voltages, 3V, than it does at higher voltages say 15V. This is why I did the earlier modelling with two different input voltages.
The component values that I have given should be safe. It may be possible to get more performance out of the MOSFET, but that would require bench testing.
In a load like this, the amount you have to change the gate voltage is small. If the transconductance of the MOSFET is 5, that is a change in drain current of 5A for a 1V change in gate voltage. To increase the output current by 5A you have increase the voltage on Ciss by 1V and decrease the voltage on Crss by 1V.
If you wanted to switch this MOSFET with a 400V drain voltage, you would have to charge Ciss with 10V and discharge Crss by 400V, much bigger changes and therefore higher currents.
Hi Jay_Diddy_B and others,
I was wondering how the loop would change if instead of Fets Bjts were used.
The reason I'm asking is that I have recently come in the possession of a somewhat old multi
channel electronic load using the good old 2N3055 as the pass elements. The control circuit
on these however is a bit crude and non-dynamic and the single turn wire wound pots are shot, so I would like to update it a bit.
Since the beta of the 2n3055 is so low on the biggest channels (9 pass elements, 300w) there are two driver stages, one BD237 and
one 2n3055 driving the others.
I would really like to know how this added gain affects the control loop so I can design a nice new driver board.
Jay,
Is it ok to replace the pulse generator part with this highlighted ones using simple 555 ics ? without disrupting the control loop ?
I just love the extra adjustabilities like the freq and pulse width.