Mod A : (0x34) 16750A Logic Analyzer (Master)
Summary Test Name #Tests #Fails
------------------------------------------------------
passed cpldRegTest 2 0
passed testLoadFPGA 2 0
passed fpgaRegTest 2 0
passed dataBusTest 2 0
passed addrBusTest 2 0
passed hwMemoryCellTest 2 0
passed unloadTest 2 0
passed dmaTest 2 0
passed sleepTest 2 0
passed searchTest 2 0
passed chipRegTest 1 0
FAILED anlyBusTest 1 1
FAILED clksTest 1 1
FAILED measAnlyBusTiming 1 1
passed bpClkTest 1 0
passed cmpTest 3 0
passed icrTest 1 0
passed flagTest 1 0
passed armTest 1 0
passed calTest 1 0
passed zoomDataTest 1 0
passed zoomMasterTest 1 0
passed fisoRedundancyTest 1 0
FAILED zoomAcqTest 17 3
passed zoomChipSelTest 5 0
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2
In the pv output "Chip 8" and "Chip 9" refer to the acquisition ASICs.
Please post (attach) your output from pv with "d r=9" turned on so we can have some context. At the moment, the output from anlyBusTest and clksTest will do.
Stage 1 is 0x0,000,0000 0x0,000,0000
#!/usr/local/bin/bash
# export PVRESULTLEVEL=9
# export PVDEBUGLEVEL=9
(
sleep 5
while true; do
echo "s e"
echo "x anlyBusTest"
sleep 1
done
) | pv
Another thing you might try...
You'll notice that there are numerous 33R resistor networks between U52 and the memory. They are for series termination for the control and data signals leading to the memory. I've had several cases of open single resistors in other areas, so it might be worth checking these resistor networks. The control signals appear to be mostly on the resistor networks directly under U52 (mounted horizontally). The data signals appear to be mostly on the ones mounted vertically on the top and bottom. But I would probably check them all anyway near U52 since it's very easy to do.
A further thought on this... You should note that the memory chips all passed previous read/write tests without error. The problem appears to be when the acquisition chips are in charge of writing to the memory. The previous tests, I believe, are done through the bus interface (Altera) FPGAs.
A further thought on this... You should note that the memory chips all passed previous read/write tests without error. The problem appears to be when the acquisition chips are in charge of writing to the memory. The previous tests, I believe, are done through the bus interface (Altera) FPGAs.
From what I understand this is the first test involving memory. All further also fail.
Indeed you are right. Is there any more documentation showing what exactly is checked by which test? On a tad lower level, so I can compare it with the hardware.
The memory ICs seem to be connected only to the Virtex FPGAs, and the lines seem to be fine. So now it's tim to check what is going on between the ASICs and the big FPGA, that controlls the offending memory chip...
If you're ever in doubt, you could always lift a leg on a working memory chip and observe which tests detect it.
I have read the guide etc but I have no idea how you know what is chip 9 etc.
If you're ever in doubt, you could always lift a leg on a working memory chip and observe which tests detect it.
This is one of the ideas, that I had... But not yet . Tommorow I plan to poke some more between the ASIC and the FPGA responsible for the U50/U59.
Regards!
Lifted DQ1 (pin 4) of U59 (memory MT48LC4M16A2) as a test on a working
board. Memory glue FPGA (Virtex) for that column is U52, acquisition
ASIC for that half of the board is U45.
pv> x modtests
Mod C: TEST passed # "cpldRegTest" (1, 0, 1)
Mod C: TEST passed # "testLoadFPGA" (1, 0, 1)
Mod C: TEST passed # "fpgaRegTest" (1, 0, 1)
Mod C: TEST FAILED # "dataBusTest" (1, 1, -1)
Mod C: TEST FAILED # "addrBusTest" (1, 1, -1)
Mod C: TEST FAILED # "hwMemoryCellTest" (1, 1, -1)
Mod C: TEST FAILED # "unloadTest" (1, 1, -1)
Mod C: TEST FAILED # "dmaTest" (1, 1, -1)
Mod C: TEST FAILED # "sleepTest" (1, 1, -1)
Mod C: TEST passed # "searchTest" (1, 0, 1)
Mod C: TEST passed # "chipRegTest" (1, 0, 1)
Mod C: TEST FAILED # "anlyBusTest" (1, 1, -1)
Mod C: TEST FAILED # "clksTest" (1, 1, -1)
Mod C: TEST FAILED # "measAnlyBusTiming" (1, 1, -1)
Mod C: TEST passed # "bpClkTest" (1, 0, 1)
Mod C: TEST passed # "cmpTest" (1, 0, 1)
Mod C: TEST passed # "icrTest" (1, 0, 1)
Mod C: TEST passed # "flagTest" (1, 0, 1)
Mod C: TEST passed # "armTest" (1, 0, 1)
Mod C: TEST passed # "calTest" (1, 0, 1)
Mod C: TEST passed # "zoomDataTest" (1, 0, 1)
Mod C: TEST passed # "zoomMasterTest" (1, 0, 1)
Mod C: TEST passed # "fisoRedundancyTest" (1, 0, 1)
Mod C: TEST passed # "zoomAcqTest" (1, 0, 1)
Mod C: TEST passed # "zoomChipSelTest" (1, 0, 1)
pv> d r=9
debugLevel=0, mode=0, resultLevel=9
pv> x dataBusTest
Slot C, Data Failures, chip 9, bank 0, port 2, exp=40000000, act=00000000, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFFFFE, act=BFFFFFFE, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFFFFD, act=BFFFFFFD, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFFFFB, act=BFFFFFFB, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFFFF7, act=BFFFFFF7, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFFFEF, act=BFFFFFEF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFFFDF, act=BFFFFFDF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFFFBF, act=BFFFFFBF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFFF7F, act=BFFFFF7F, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFFEFF, act=BFFFFEFF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFFDFF, act=BFFFFDFF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFFBFF, act=BFFFFBFF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFF7FF, act=BFFFF7FF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFEFFF, act=BFFFEFFF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFDFFF, act=BFFFDFFF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFFBFFF, act=BFFFBFFF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFF7FFF, act=BFFF7FFF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFEFFFF, act=BFFEFFFF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFDFFFF, act=BFFDFFFF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFFBFFFF, act=BFFBFFFF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFF7FFFF, act=BFF7FFFF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFEFFFFF, act=BFEFFFFF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFDFFFFF, act=BFDFFFFF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FFBFFFFF, act=BFBFFFFF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FF7FFFFF, act=BF7FFFFF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FEFFFFFF, act=BEFFFFFF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FDFFFFFF, act=BDFFFFFF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=FBFFFFFF, act=BBFFFFFF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=F7FFFFFF, act=B7FFFFFF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=EFFFFFFF, act=AFFFFFFF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=DFFFFFFF, act=9FFFFFFF, Mems U59
Slot C, Data Failures, chip 9, bank 0, port 2, exp=7FFFFFFF, act=3FFFFFFF, Mems U59
Slot C, Data Error, chip 9, bank 0, port 2, bits=40000000, Mems U59
Mod C: TEST FAILED # "dataBusTest" (2, 2, -1)
pv> x addrBusTest
Slot C, chip 9, port 2, bank 0, addr=00000001, exp=FFFEFFFE, act=BFFEFFFE, Mems U59
Slot C, chip 9, port 2, bank 0, addr=00000002, exp=FFFCFFFC, act=BFFCFFFC, Mems U59
Slot C, chip 9, port 2, bank 0, addr=00000004, exp=FFFAFFFA, act=BFFAFFFA, Mems U59
Slot C, chip 9, port 2, bank 0, addr=00000008, exp=FFF6FFF6, act=BFF6FFF6, Mems U59
Slot C, chip 9, port 2, bank 0, addr=00000010, exp=FFEEFFEE, act=BFEEFFEE, Mems U59
Slot C, chip 9, port 2, bank 0, addr=00000020, exp=FFDEFFDE, act=BFDEFFDE, Mems U59
Slot C, chip 9, port 2, bank 0, addr=00000040, exp=FFBEFFBE, act=BFBEFFBE, Mems U59
Slot C, chip 9, port 2, bank 0, addr=00000080, exp=FF7EFF7E, act=BF7EFF7E, Mems U59
Slot C, chip 9, port 2, bank 0, addr=00000100, exp=FEFEFEFE, act=BEFEFEFE, Mems U59
Slot C, chip 9, port 2, bank 0, addr=00000200, exp=FDFEFDFE, act=BDFEFDFE, Mems U59
Slot C, chip 9, port 2, bank 0, addr=00000400, exp=FBFEFBFE, act=BBFEFBFE, Mems U59
Slot C, chip 9, port 2, bank 0, addr=00000800, exp=F7FEF7FE, act=B7FEF7FE, Mems U59
Slot C, chip 9, port 2, bank 0, addr=00001000, exp=EFFEEFFE, act=AFFEEFFE, Mems U59
Slot C, chip 9, port 2, bank 0, addr=00002000, exp=DFFEDFFE, act=9FFEDFFE, Mems U59
Slot C, chip 9, port 2, bank 0, addr=00008000, exp=7FFE7FFE, act=3FFE7FFE, Mems U59
Slot C, chip 9, port 2, bank 0, addr=00010000, exp=FFFCFFFC, act=BFFCFFFC, Mems U59
Slot C, chip 9, port 2, bank 0, addr=00020000, exp=FFFDFFFD, act=BFFDFFFD, Mems U59
Slot C, chip 9, port 2, bank 0, addr=00040000, exp=FFF9FFF9, act=BFF9FFF9, Mems U59
Slot C, chip 9, port 2, bank 0, addr=00080000, exp=FFF5FFF5, act=BFF5FFF5, Mems U59
Slot C, chip 9, port 2, bank 0, addr=00100000, exp=FFEDFFED, act=BFEDFFED, Mems U59
Slot C, chip 9, port 2, bank 0, addr=00200000, exp=FFDDFFDD, act=BFDDFFDD, Mems U59
Slot C, chip 9, port 2, bank 0, addr=003FBFFF, exp=40014001, act=00014001, Mems U59
Address bits stuck:
Slot C, Failed address test, Memory U59
Slot C, chip 9, port=2, bank 0, AddrBitsHigh=0004000, Mems U59 U50
Mod C: TEST FAILED # "addrBusTest" (2, 2, -1)
pv> x hwMemoryCellTest
Slot C, SDRAM Fpga 0 done. Num trys = 50.
Slot C, SDRAM Fpga 2 done. Num trys = 50.
Slot C, SDRAM Fpga 1 done. Num trys = 74.
Slot C, fpga U52, port 0, Failed: Top Bank, Hi Word, Mem U59.
Slot C, fpga U52, port 0, Failed: Bottom Bank, Hi Word, Mem U89.
Slot C, SDRAM Fpga 3 done. Num trys = 74.
Mod C: TEST FAILED # "hwMemoryCellTest" (2, 2, -1)
pv> x unloadTest
Slot C, Chip 9: SDRAM Data Only Unload Test ...
Slot C, Chip 9, SDRAM U59: MAC:0x000000, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000002, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000003, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000004, bank 0, port 2 MSW, exp:0xfffb actual:0xbffb
Slot C, Chip 9, SDRAM U59: MAC:0x000005, bank 0, port 2 MSW, exp:0xffbf actual:0xbfbf
Slot C, Chip 9, SDRAM U59: MAC:0x000006, bank 0, port 2 MSW, exp:0xfbff actual:0xbbff
Slot C, Chip 9, SDRAM U59: MAC:0x000008, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000009, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x00000a, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0xfffe actual:0xbffe
Slot C, Chip 9, SDRAM U59: MAC:0x00000d, bank 0, port 2 MSW, exp:0xffef actual:0xbfef
Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0xfeff actual:0xbeff
Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0xefff actual:0xafff
Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000011, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9: SDRAM Data Only Unload Test Failed!
Slot C, Chip 9: SDRAM Count Only Unload Test ...
Slot C, Chip 9: Interleaved Data & Count Unload Test ...
Slot C, Chip 9, SDRAM U59: MAC:0x000000, bank 0, port 2 MSW, exp:0x54aa actual:0x14aa
Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0x52aa actual:0x12aa
Slot C, Chip 9, SDRAM U59: MAC:0x000002, bank 0, port 2 MSW, exp:0x4aaa actual:0x0aaa
Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0xd555 actual:0x9555
Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0x5555 actual:0x1555
Slot C, Chip 9, SDRAM U59: MAC:0x00000d, bank 0, port 2 MSW, exp:0x5554 actual:0x1554
Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0x5552 actual:0x1552
Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0x554a actual:0x154a
Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0x552a actual:0x152a
Slot C, Chip 9, SDRAM U59: MAC:0x000011, bank 0, port 2 MSW, exp:0x54aa actual:0x14aa
Slot C, Chip 9, SDRAM U59: MAC:0x000012, bank 0, port 2 MSW, exp:0x52aa actual:0x12aa
Slot C, Chip 9, SDRAM U59: MAC:0x000013, bank 0, port 2 MSW, exp:0x4aaa actual:0x0aaa
Slot C, Chip 9, SDRAM U59: MAC:0x00001c, bank 0, port 2 MSW, exp:0xd555 actual:0x9555
Slot C, Chip 9, SDRAM U59: MAC:0x00001d, bank 0, port 2 MSW, exp:0x5555 actual:0x1555
Slot C, Chip 9, SDRAM U59: MAC:0x00001e, bank 0, port 2 MSW, exp:0x5554 actual:0x1554
Slot C, Chip 9, SDRAM U59: MAC:0x00001f, bank 0, port 2 MSW, exp:0x5552 actual:0x1552
Slot C, Chip 9, SDRAM U59: MAC:0x000020, bank 0, port 2 MSW, exp:0x554a actual:0x154a
Slot C, Chip 9: Interleaved Data & Count Unload Test Failed!
Slot C, Chip 9: SDRAM Data Unload Modes Test Failed!
Slot C, Chip 8: SDRAM Data Only Unload Test ...
Slot C, Chip 8: SDRAM Count Only Unload Test ...
Slot C, Chip 8: Interleaved Data & Count Unload Test ...
Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
Mod C: TEST FAILED # "unloadTest" (2, 2, -1)
pv> x dmaTest
Slot C, Chip 9: DMA Data Only Unload Test ...
Slot C, Chip 9, SDRAM U59: MAC:0x3fe807, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe818, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe829, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe83a, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe84b, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe85c, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe86d, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe87e, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe88f, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe8a0, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe8b1, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe8c2, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe8d3, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe8e4, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe8f5, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe906, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe917, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9: DMA Data Only Test Failed!
Slot C, Chip 9: DMA Count Only Unload Test ...
Slot C, Chip 9: DMA Interleaved Data & Count Test ...
Slot C, Chip 9, SDRAM U59: MAC:0x3fe800, bank 0, port 2 MSW, exp:0x54aa actual:0x14aa
Slot C, Chip 9, SDRAM U59: MAC:0x3fe801, bank 0, port 2 MSW, exp:0x52aa actual:0x12aa
Slot C, Chip 9, SDRAM U59: MAC:0x3fe802, bank 0, port 2 MSW, exp:0x4aaa actual:0x0aaa
Slot C, Chip 9, SDRAM U59: MAC:0x3fe80b, bank 0, port 2 MSW, exp:0xd555 actual:0x9555
Slot C, Chip 9, SDRAM U59: MAC:0x3fe80c, bank 0, port 2 MSW, exp:0x5555 actual:0x1555
Slot C, Chip 9, SDRAM U59: MAC:0x3fe80d, bank 0, port 2 MSW, exp:0x5554 actual:0x1554
Slot C, Chip 9, SDRAM U59: MAC:0x3fe80e, bank 0, port 2 MSW, exp:0x5552 actual:0x1552
Slot C, Chip 9, SDRAM U59: MAC:0x3fe80f, bank 0, port 2 MSW, exp:0x554a actual:0x154a
Slot C, Chip 9, SDRAM U59: MAC:0x3fe810, bank 0, port 2 MSW, exp:0x552a actual:0x152a
Slot C, Chip 9, SDRAM U59: MAC:0x3fe811, bank 0, port 2 MSW, exp:0x54aa actual:0x14aa
Slot C, Chip 9, SDRAM U59: MAC:0x3fe812, bank 0, port 2 MSW, exp:0x52aa actual:0x12aa
Slot C, Chip 9, SDRAM U59: MAC:0x3fe813, bank 0, port 2 MSW, exp:0x4aaa actual:0x0aaa
Slot C, Chip 9, SDRAM U59: MAC:0x3fe81c, bank 0, port 2 MSW, exp:0xd555 actual:0x9555
Slot C, Chip 9, SDRAM U59: MAC:0x3fe81d, bank 0, port 2 MSW, exp:0x5555 actual:0x1555
Slot C, Chip 9, SDRAM U59: MAC:0x3fe81e, bank 0, port 2 MSW, exp:0x5554 actual:0x1554
Slot C, Chip 9, SDRAM U59: MAC:0x3fe81f, bank 0, port 2 MSW, exp:0x5552 actual:0x1552
Slot C, Chip 9, SDRAM U59: MAC:0x3fe820, bank 0, port 2 MSW, exp:0x554a actual:0x154a
Slot C, Chip 9: DMA Interleaved Data & Count Test Failed!
> Slot C, Chip 9: DMA Unload Modes Test Failed!
Slot C, Chip 8: DMA Data Only Unload Test ...
Slot C, Chip 8: DMA Count Only Unload Test ...
Slot C, Chip 8: DMA Interleaved Data & Count Test ...
Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
Mod C: TEST FAILED # "dmaTest" (2, 2, -1)
pv> x sleepTest
Slot C, Chip 9, SDRAM U59: MAC:0x000000, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000002, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000003, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000004, bank 0, port 2 MSW, exp:0xfffb actual:0xbffb
Slot C, Chip 9, SDRAM U59: MAC:0x000005, bank 0, port 2 MSW, exp:0xffbf actual:0xbfbf
Slot C, Chip 9, SDRAM U59: MAC:0x000006, bank 0, port 2 MSW, exp:0xfbff actual:0xbbff
Slot C, Chip 9, SDRAM U59: MAC:0x000008, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000009, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x00000a, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0xfffe actual:0xbffe
Slot C, Chip 9, SDRAM U59: MAC:0x00000d, bank 0, port 2 MSW, exp:0xffef actual:0xbfef
Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0xfeff actual:0xbeff
Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0xefff actual:0xafff
Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000011, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9: Top bank check failed before Sleep mode.
Mod C: TEST FAILED # "sleepTest" (2, 2, -1)
pv> x anlyBusTest
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=40000000, act=00000000
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFFE, act=BFFFFFFE
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFFD, act=BFFFFFFD
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFFB, act=BFFFFFFB
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFF7, act=BFFFFFF7
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFEF, act=BFFFFFEF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFDF, act=BFFFFFDF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFBF, act=BFFFFFBF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFF7F, act=BFFFFF7F
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFEFF, act=BFFFFEFF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFDFF, act=BFFFFDFF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFBFF, act=BFFFFBFF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFF7FF, act=BFFFF7FF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFEFFF, act=BFFFEFFF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFDFFF, act=BFFFDFFF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFBFFF, act=BFFFBFFF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFF7FFF, act=BFFF7FFF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFEFFFF, act=BFFEFFFF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFDFFFF, act=BFFDFFFF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFBFFFF, act=BFFBFFFF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFF7FFFF, act=BFF7FFFF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFEFFFFF, act=BFEFFFFF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFDFFFFF, act=BFDFFFFF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFBFFFFF, act=BFBFFFFF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FF7FFFFF, act=BF7FFFFF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FEFFFFFF, act=BEFFFFFF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FDFFFFFF, act=BDFFFFFF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FBFFFFFF, act=BBFFFFFF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=F7FFFFFF, act=B7FFFFFF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=EFFFFFFF, act=AFFFFFFF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=DFFFFFFF, act=9FFFFFFF
Slot C, Analysis Chip Data Bit Failed, chip 9, port 2, exp=7FFFFFFF, act=3FFFFFFF
Slot C, Analysis Chip Data Bit Error, chip 9, port 2, bits=40000000
Mod C: TEST FAILED # "anlyBusTest" (2, 2, -1)
pv> x clksTest
TEST 1: Master Clock from CHIP 9 ...
Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
Slot C, Chip 9, SDRAM U59: MAC:0x000004, bank 0, port 2 MSW, exp:0x4926 actual:0x0926
Slot C, Chip 9, SDRAM U59: MAC:0x000007, bank 0, port 2 MSW, exp:0x6492 actual:0x2492
Slot C, Chip 9, SDRAM U59: MAC:0x000008, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0x4992 actual:0x0992
Slot C, Chip 9, SDRAM U59: MAC:0x000012, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
Slot C, Chip 9, SDRAM U59: MAC:0x000015, bank 0, port 2 MSW, exp:0x4926 actual:0x0926
Slot C, Chip 9, SDRAM U59: MAC:0x000018, bank 0, port 2 MSW, exp:0x6492 actual:0x2492
Slot C, Chip 9, SDRAM U59: MAC:0x000019, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
Slot C, Chip 9, SDRAM U59: MAC:0x00001c, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
Slot C, Chip 9, SDRAM U59: MAC:0x00001f, bank 0, port 2 MSW, exp:0x4992 actual:0x0992
Slot C, Chip 9, SDRAM U59: MAC:0x000023, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
Slot C, Chip 9, SDRAM U59: MAC:0x000026, bank 0, port 2 MSW, exp:0x4926 actual:0x0926
Slot C, Chip 9, SDRAM U59: MAC:0x000029, bank 0, port 2 MSW, exp:0x6492 actual:0x2492
Slot C, Chip 9, SDRAM U59: MAC:0x00002a, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
Slot C, Chip 9, SDRAM U59: MAC:0x00002d, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
> Slot C, Chip 9: Master Clock from Chip 9 Test Failed!
Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
TEST 2: Slave Clock from CHIP 9 ...
Slot C, Chip 9, SDRAM U59: MAC:0x000000, bank 0, port 2 MSW, exp:0xe739 actual:0xa739
Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0x739c actual:0x339c
Slot C, Chip 9, SDRAM U59: MAC:0x000004, bank 0, port 2 MSW, exp:0xce73 actual:0x8e73
Slot C, Chip 9, SDRAM U59: MAC:0x000005, bank 0, port 2 MSW, exp:0xe733 actual:0xa733
Slot C, Chip 9, SDRAM U59: MAC:0x000006, bank 0, port 2 MSW, exp:0x7339 actual:0x3339
Slot C, Chip 9, SDRAM U59: MAC:0x00000a, bank 0, port 2 MSW, exp:0xce73 actual:0x8e73
Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0xe739 actual:0xa739
Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0x739c actual:0x339c
Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0xcce7 actual:0x8ce7
Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0xce73 actual:0x8e73
Slot C, Chip 9, SDRAM U59: MAC:0x000011, bank 0, port 2 MSW, exp:0xe739 actual:0xa739
Slot C, Chip 9, SDRAM U59: MAC:0x000012, bank 0, port 2 MSW, exp:0x739c actual:0x339c
Slot C, Chip 9, SDRAM U59: MAC:0x000015, bank 0, port 2 MSW, exp:0xce73 actual:0x8e73
Slot C, Chip 9, SDRAM U59: MAC:0x000016, bank 0, port 2 MSW, exp:0xe733 actual:0xa733
Slot C, Chip 9, SDRAM U59: MAC:0x000017, bank 0, port 2 MSW, exp:0x7339 actual:0x3339
Slot C, Chip 9, SDRAM U59: MAC:0x00001b, bank 0, port 2 MSW, exp:0xce73 actual:0x8e73
Slot C, Chip 9, SDRAM U59: MAC:0x00001c, bank 0, port 2 MSW, exp:0xe739 actual:0xa739
> Slot C, Chip 9: Slave Clock from Chip 9 Test Failed!
Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
TEST 3: Master Clock from CHIP 8 thru Chip 9 ...
Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0xb6db actual:0xf6db
Slot C, Chip 9, SDRAM U59: MAC:0x000003, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
Slot C, Chip 9, SDRAM U59: MAC:0x000005, bank 0, port 2 MSW, exp:0x6d9b actual:0x2d9b
Slot C, Chip 9, SDRAM U59: MAC:0x000006, bank 0, port 2 MSW, exp:0xd9b6 actual:0x99b6
Slot C, Chip 9, SDRAM U59: MAC:0x000009, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
Slot C, Chip 9, SDRAM U59: MAC:0x00000a, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
Slot C, Chip 9, SDRAM U59: MAC:0x00000d, bank 0, port 2 MSW, exp:0xdb66 actual:0x9b66
Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0x66db actual:0x26db
Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
Slot C, Chip 9, SDRAM U59: MAC:0x000011, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
Slot C, Chip 9, SDRAM U59: MAC:0x000013, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
Slot C, Chip 9, SDRAM U59: MAC:0x000014, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
Slot C, Chip 9, SDRAM U59: MAC:0x000016, bank 0, port 2 MSW, exp:0x6d9b actual:0x2d9b
Slot C, Chip 9, SDRAM U59: MAC:0x000017, bank 0, port 2 MSW, exp:0xd9b6 actual:0x99b6
Slot C, Chip 9, SDRAM U59: MAC:0x00001a, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
Slot C, Chip 9, SDRAM U59: MAC:0x00001b, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
> Slot C, Chip 9: Master Clock from Chip 8 thru Chip 9 Test Failed!
Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
TEST 4: Slave Clock from CHIP 8 thru Chip 9 ...
Slot C, Chip 9, SDRAM U59: MAC:0x000000, bank 0, port 2 MSW, exp:0x18c6 actual:0x58c6
Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0x8c63 actual:0xcc63
Slot C, Chip 9, SDRAM U59: MAC:0x000002, bank 0, port 2 MSW, exp:0xc631 actual:0x8631
Slot C, Chip 9, SDRAM U59: MAC:0x000003, bank 0, port 2 MSW, exp:0x6318 actual:0x2318
Slot C, Chip 9, SDRAM U59: MAC:0x000007, bank 0, port 2 MSW, exp:0xcc63 actual:0x8c63
Slot C, Chip 9, SDRAM U59: MAC:0x000008, bank 0, port 2 MSW, exp:0xc631 actual:0x8631
Slot C, Chip 9, SDRAM U59: MAC:0x000009, bank 0, port 2 MSW, exp:0x6318 actual:0x2318
Slot C, Chip 9, SDRAM U59: MAC:0x00000d, bank 0, port 2 MSW, exp:0xc633 actual:0x8633
Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0x6331 actual:0x2331
Slot C, Chip 9, SDRAM U59: MAC:0x000013, bank 0, port 2 MSW, exp:0xc631 actual:0x8631
Slot C, Chip 9, SDRAM U59: MAC:0x000014, bank 0, port 2 MSW, exp:0x6318 actual:0x2318
Slot C, Chip 9, SDRAM U59: MAC:0x000018, bank 0, port 2 MSW, exp:0xcc63 actual:0x8c63
Slot C, Chip 9, SDRAM U59: MAC:0x000019, bank 0, port 2 MSW, exp:0xc631 actual:0x8631
Slot C, Chip 9, SDRAM U59: MAC:0x00001a, bank 0, port 2 MSW, exp:0x6318 actual:0x2318
Slot C, Chip 9, SDRAM U59: MAC:0x00001e, bank 0, port 2 MSW, exp:0xc633 actual:0x8633
Slot C, Chip 9, SDRAM U59: MAC:0x00001f, bank 0, port 2 MSW, exp:0x6331 actual:0x2331
Slot C, Chip 9, SDRAM U59: MAC:0x000024, bank 0, port 2 MSW, exp:0xc631 actual:0x8631
> Slot C, Chip 9: Slave Clock from Chip 8 thru Chip 9 Test Failed!
Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
TEST 5: Psync Clock from CHIP 8 thru CHIP 9 ...
Slot C, Chip 9, SDRAM U59: MAC:0x000000, bank 0, port 2 MSW, exp:0xb6db actual:0xf6db
Slot C, Chip 9, SDRAM U59: MAC:0x000002, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
Slot C, Chip 9, SDRAM U59: MAC:0x000004, bank 0, port 2 MSW, exp:0x6db7 actual:0x2db7
Slot C, Chip 9, SDRAM U59: MAC:0x000005, bank 0, port 2 MSW, exp:0xdb76 actual:0x9b76
Slot C, Chip 9, SDRAM U59: MAC:0x000007, bank 0, port 2 MSW, exp:0x76db actual:0x36db
Slot C, Chip 9, SDRAM U59: MAC:0x000008, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
Slot C, Chip 9, SDRAM U59: MAC:0x000009, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0x6ddb actual:0x2ddb
Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0xddb6 actual:0x9db6
Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
Slot C, Chip 9, SDRAM U59: MAC:0x000012, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
Slot C, Chip 9, SDRAM U59: MAC:0x000013, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
Slot C, Chip 9, SDRAM U59: MAC:0x000015, bank 0, port 2 MSW, exp:0x6db7 actual:0x2db7
Slot C, Chip 9, SDRAM U59: MAC:0x000016, bank 0, port 2 MSW, exp:0xdb76 actual:0x9b76
Slot C, Chip 9, SDRAM U59: MAC:0x000018, bank 0, port 2 MSW, exp:0x76db actual:0x36db
> Slot C, Chip 9: Slave Clock from Chip 9 thru Chip 8 Test Failed!
Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
TEST 6: Master Clock from CHIP 8 ...
TEST 7: Slave Clock from CHIP 8 ...
TEST 8: Master Clock from CHIP 9 thru CHIP 8 ...
TEST 9: Slave Clock from CHIP 9 thru CHIP 8 ...
TEST 10: Psync Clock from CHIP 9 thru CHIP 8 ...
TEST 11: Poststore Counter Test ...
Mod C: TEST FAILED # "clksTest" (2, 2, -1)
pv>x measAnlyBusTiming
Chip 9: Maximum Time Range = 6300
Slot Chip FineT Port SuTime WinSize SuErrBits HldErrBits STap HTap
==== ==== ===== ==== ======= ======= ========== ========== ==== ====
C 9 100 0 5600 > 700 04080002 FFFFFFFF 7 0
C 9 100 1 5300 >1000 00000240 FFFF6DBB 10 0
C 9 100 2 0 >6300 40000000 443A6FFF 63 0
FAILED: Slot:C Chip:9 Port:2 Setup: 0 (Limit > 3000), Setup Tap = 63 (Limit < 20), Bits:40000000
C 9 100 3 5600 > 700 00412000 FFFFFFFF 7 0
C 9 100 B -1 > 0 0000 FFFF 999 999
Chip 8: Maximum Time Range = 5985
Slot Chip FineT Port SuTime WinSize SuErrBits HldErrBits STap HTap
==== ==== ===== ==== ======= ======= ========== ========== ==== ====
C 8 95 0 5225 > 760 00080000 FFFFFFFF 8 0
C 8 95 1 5035 > 950 00000240 FFFFEDBB 10 0
C 8 95 2 4940 >1045 88000000 043A6FFF 11 0
C 8 95 3 5320 > 665 00412000 FFFFFFFF 7 0
C 8 95 B -1 > 0 0000 FFFF 999 999
Mod C: TEST FAILED # "measAnlyBusTiming" (3, 3, -1)
------------------------------------------------------------
Some of these tests produce more info with resultLevel 10...
pv> d r=10
debugLevel=0, mode=1, resultLevel=10
pv> x unloadTest
Slot C, Chip 9: SDRAM Data Only Unload Test ...
-- Writing Full Channel Normal Data --
-- Writing Normal Bonus Data --
-- Reading Full Channel Normal Data --
Slot C, Chip 9, SDRAM U59: MAC:0x000000, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000002, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000003, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000004, bank 0, port 2 MSW, exp:0xfffb actual:0xbffb
Slot C, Chip 9, SDRAM U59: MAC:0x000005, bank 0, port 2 MSW, exp:0xffbf actual:0xbfbf
Slot C, Chip 9, SDRAM U59: MAC:0x000006, bank 0, port 2 MSW, exp:0xfbff actual:0xbbff
Slot C, Chip 9, SDRAM U59: MAC:0x000008, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000009, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x00000a, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0xfffe actual:0xbffe
Slot C, Chip 9, SDRAM U59: MAC:0x00000d, bank 0, port 2 MSW, exp:0xffef actual:0xbfef
Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0xfeff actual:0xbeff
Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0xefff actual:0xafff
Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000011, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
-- Reading Bonus Data --
Slot C, Chip 9: SDRAM Data Only Unload Test Failed!
Slot C, Chip 9: SDRAM Count Only Unload Test ...
-- Writing Count Data --
-- Reading Count Data --
Slot C, Chip 9: Interleaved Data & Count Unload Test ...
-- Writing Interleaved Data & Tags --
-- Writing Interleaved Bonus Data --
-- Reading Full Channel Normal Data --
Slot C, Chip 9, SDRAM U59: MAC:0x000000, bank 0, port 2 MSW, exp:0x54aa actual:0x14aa
Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0x52aa actual:0x12aa
Slot C, Chip 9, SDRAM U59: MAC:0x000002, bank 0, port 2 MSW, exp:0x4aaa actual:0x0aaa
Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0xd555 actual:0x9555
Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0x5555 actual:0x1555
Slot C, Chip 9, SDRAM U59: MAC:0x00000d, bank 0, port 2 MSW, exp:0x5554 actual:0x1554
Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0x5552 actual:0x1552
Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0x554a actual:0x154a
Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0x552a actual:0x152a
Slot C, Chip 9, SDRAM U59: MAC:0x000011, bank 0, port 2 MSW, exp:0x54aa actual:0x14aa
Slot C, Chip 9, SDRAM U59: MAC:0x000012, bank 0, port 2 MSW, exp:0x52aa actual:0x12aa
Slot C, Chip 9, SDRAM U59: MAC:0x000013, bank 0, port 2 MSW, exp:0x4aaa actual:0x0aaa
Slot C, Chip 9, SDRAM U59: MAC:0x00001c, bank 0, port 2 MSW, exp:0xd555 actual:0x9555
Slot C, Chip 9, SDRAM U59: MAC:0x00001d, bank 0, port 2 MSW, exp:0x5555 actual:0x1555
Slot C, Chip 9, SDRAM U59: MAC:0x00001e, bank 0, port 2 MSW, exp:0x5554 actual:0x1554
Slot C, Chip 9, SDRAM U59: MAC:0x00001f, bank 0, port 2 MSW, exp:0x5552 actual:0x1552
Slot C, Chip 9, SDRAM U59: MAC:0x000020, bank 0, port 2 MSW, exp:0x554a actual:0x154a
-- Reading Bonus Data --
-- Reading Count Data --
Slot C, Chip 9: Interleaved Data & Count Unload Test Failed!
Slot C, Chip 9: SDRAM Data Unload Modes Test Failed!
Slot C, Chip 8: SDRAM Data Only Unload Test ...
-- Writing Full Channel Normal Data --
-- Writing Normal Bonus Data --
-- Reading Full Channel Normal Data --
-- Reading Bonus Data --
Slot C, Chip 8: SDRAM Count Only Unload Test ...
-- Writing Count Data --
-- Reading Count Data --
Slot C, Chip 8: Interleaved Data & Count Unload Test ...
-- Writing Interleaved Data & Tags --
-- Writing Interleaved Bonus Data --
-- Reading Full Channel Normal Data --
-- Reading Bonus Data --
-- Reading Count Data --
Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
Mod C: TEST FAILED # "unloadTest" (6, 6, -1)
pv> x dmaTest
Slot C, Chip 9: DMA Data Only Unload Test ...
-- Writing Full Channel Normal Data --
-- Writing Normal Bonus Data --
-- Reading Normal Data Using DMA --
Slot C, Chip 9, SDRAM U59: MAC:0x3fe807, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe818, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe829, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe83a, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe84b, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe85c, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe86d, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe87e, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe88f, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe8a0, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe8b1, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe8c2, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe8d3, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe8e4, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe8f5, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe906, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
Slot C, Chip 9, SDRAM U59: MAC:0x3fe917, bank 0, port 2 MSW, exp:0x4000 actual:0x0000
-- Reading Bonus Data Using DMA --
Slot C, Chip 9: DMA Data Only Test Failed!
Slot C, Chip 9: DMA Count Only Unload Test ...
-- Writing Count Data --
-- Reading Count Data Using DMA --
Slot C, Chip 9: DMA Interleaved Data & Count Test ...
-- Writing Interleaved Data & Tags --
-- Writing Interleaved Bonus Data --
-- Reading Normal Data Using DMA --
Slot C, Chip 9, SDRAM U59: MAC:0x3fe800, bank 0, port 2 MSW, exp:0x54aa actual:0x14aa
Slot C, Chip 9, SDRAM U59: MAC:0x3fe801, bank 0, port 2 MSW, exp:0x52aa actual:0x12aa
Slot C, Chip 9, SDRAM U59: MAC:0x3fe802, bank 0, port 2 MSW, exp:0x4aaa actual:0x0aaa
Slot C, Chip 9, SDRAM U59: MAC:0x3fe80b, bank 0, port 2 MSW, exp:0xd555 actual:0x9555
Slot C, Chip 9, SDRAM U59: MAC:0x3fe80c, bank 0, port 2 MSW, exp:0x5555 actual:0x1555
Slot C, Chip 9, SDRAM U59: MAC:0x3fe80d, bank 0, port 2 MSW, exp:0x5554 actual:0x1554
Slot C, Chip 9, SDRAM U59: MAC:0x3fe80e, bank 0, port 2 MSW, exp:0x5552 actual:0x1552
Slot C, Chip 9, SDRAM U59: MAC:0x3fe80f, bank 0, port 2 MSW, exp:0x554a actual:0x154a
Slot C, Chip 9, SDRAM U59: MAC:0x3fe810, bank 0, port 2 MSW, exp:0x552a actual:0x152a
Slot C, Chip 9, SDRAM U59: MAC:0x3fe811, bank 0, port 2 MSW, exp:0x54aa actual:0x14aa
Slot C, Chip 9, SDRAM U59: MAC:0x3fe812, bank 0, port 2 MSW, exp:0x52aa actual:0x12aa
Slot C, Chip 9, SDRAM U59: MAC:0x3fe813, bank 0, port 2 MSW, exp:0x4aaa actual:0x0aaa
Slot C, Chip 9, SDRAM U59: MAC:0x3fe81c, bank 0, port 2 MSW, exp:0xd555 actual:0x9555
Slot C, Chip 9, SDRAM U59: MAC:0x3fe81d, bank 0, port 2 MSW, exp:0x5555 actual:0x1555
Slot C, Chip 9, SDRAM U59: MAC:0x3fe81e, bank 0, port 2 MSW, exp:0x5554 actual:0x1554
Slot C, Chip 9, SDRAM U59: MAC:0x3fe81f, bank 0, port 2 MSW, exp:0x5552 actual:0x1552
Slot C, Chip 9, SDRAM U59: MAC:0x3fe820, bank 0, port 2 MSW, exp:0x554a actual:0x154a
-- Reading Bonus Data Using DMA --
-- Reading Count Data Using DMA --
Slot C, Chip 9: DMA Interleaved Data & Count Test Failed!
> Slot C, Chip 9: DMA Unload Modes Test Failed!
Slot C, Chip 8: DMA Data Only Unload Test ...
-- Writing Full Channel Normal Data --
-- Writing Normal Bonus Data --
-- Reading Normal Data Using DMA --
-- Reading Bonus Data Using DMA --
Slot C, Chip 8: DMA Count Only Unload Test ...
-- Writing Count Data --
-- Reading Count Data Using DMA --
Slot C, Chip 8: DMA Interleaved Data & Count Test ...
-- Writing Interleaved Data & Tags --
-- Writing Interleaved Bonus Data --
-- Reading Normal Data Using DMA --
-- Reading Bonus Data Using DMA --
-- Reading Count Data Using DMA --
Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
Mod C: TEST FAILED # "dmaTest" (2, 2, -1)
pv> x sleepTest
-- Writing Full Channel Normal Data --
-- Writing Normal Bonus Data --
-- Writing Full Channel Normal Data --
-- Writing Normal Bonus Data --
-- Reading Full Channel Normal Data --
Slot C, Chip 9, SDRAM U59: MAC:0x000000, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000002, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000003, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000004, bank 0, port 2 MSW, exp:0xfffb actual:0xbffb
Slot C, Chip 9, SDRAM U59: MAC:0x000005, bank 0, port 2 MSW, exp:0xffbf actual:0xbfbf
Slot C, Chip 9, SDRAM U59: MAC:0x000006, bank 0, port 2 MSW, exp:0xfbff actual:0xbbff
Slot C, Chip 9, SDRAM U59: MAC:0x000008, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000009, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x00000a, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0xfffe actual:0xbffe
Slot C, Chip 9, SDRAM U59: MAC:0x00000d, bank 0, port 2 MSW, exp:0xffef actual:0xbfef
Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0xfeff actual:0xbeff
Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0xefff actual:0xafff
Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
Slot C, Chip 9, SDRAM U59: MAC:0x000011, bank 0, port 2 MSW, exp:0xffff actual:0xbfff
-- Reading Bonus Data --
Slot C, Chip 9: Top bank check failed before Sleep mode.
-- Reading Full Channel Normal Data --
-- Reading Bonus Data --
-- Reading Full Channel Normal Data --
-- Reading Bonus Data --
-- Reading Full Channel Normal Data --
-- Reading Bonus Data --
Mod C: TEST FAILED # "sleepTest" (1, 1, -1)
pv> x clksTest
-- Writing Full Channel Normal Data --
-- Writing Normal Bonus Data --
TEST 1: Master Clock from CHIP 9 ...
-- Reading Full Channel Normal Data --
Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
Slot C, Chip 9, SDRAM U59: MAC:0x000004, bank 0, port 2 MSW, exp:0x4926 actual:0x0926
Slot C, Chip 9, SDRAM U59: MAC:0x000007, bank 0, port 2 MSW, exp:0x6492 actual:0x2492
Slot C, Chip 9, SDRAM U59: MAC:0x000008, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0x4992 actual:0x0992
Slot C, Chip 9, SDRAM U59: MAC:0x000012, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
Slot C, Chip 9, SDRAM U59: MAC:0x000015, bank 0, port 2 MSW, exp:0x4926 actual:0x0926
Slot C, Chip 9, SDRAM U59: MAC:0x000018, bank 0, port 2 MSW, exp:0x6492 actual:0x2492
Slot C, Chip 9, SDRAM U59: MAC:0x000019, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
Slot C, Chip 9, SDRAM U59: MAC:0x00001c, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
Slot C, Chip 9, SDRAM U59: MAC:0x00001f, bank 0, port 2 MSW, exp:0x4992 actual:0x0992
Slot C, Chip 9, SDRAM U59: MAC:0x000023, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
Slot C, Chip 9, SDRAM U59: MAC:0x000026, bank 0, port 2 MSW, exp:0x4926 actual:0x0926
Slot C, Chip 9, SDRAM U59: MAC:0x000029, bank 0, port 2 MSW, exp:0x6492 actual:0x2492
Slot C, Chip 9, SDRAM U59: MAC:0x00002a, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
Slot C, Chip 9, SDRAM U59: MAC:0x00002d, bank 0, port 2 MSW, exp:0x4924 actual:0x0924
-- Reading Bonus Data --
> Slot C, Chip 9: Master Clock from Chip 9 Test Failed!
-- Reading Full Channel Normal Data --
-- Reading Bonus Data --
Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
TEST 2: Slave Clock from CHIP 9 ...
-- Reading Full Channel Normal Data --
Slot C, Chip 9, SDRAM U59: MAC:0x000000, bank 0, port 2 MSW, exp:0xe739 actual:0xa739
Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0x739c actual:0x339c
Slot C, Chip 9, SDRAM U59: MAC:0x000004, bank 0, port 2 MSW, exp:0xce73 actual:0x8e73
Slot C, Chip 9, SDRAM U59: MAC:0x000005, bank 0, port 2 MSW, exp:0xe733 actual:0xa733
Slot C, Chip 9, SDRAM U59: MAC:0x000006, bank 0, port 2 MSW, exp:0x7339 actual:0x3339
Slot C, Chip 9, SDRAM U59: MAC:0x00000a, bank 0, port 2 MSW, exp:0xce73 actual:0x8e73
Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0xe739 actual:0xa739
Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0x739c actual:0x339c
Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0xcce7 actual:0x8ce7
Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0xce73 actual:0x8e73
Slot C, Chip 9, SDRAM U59: MAC:0x000011, bank 0, port 2 MSW, exp:0xe739 actual:0xa739
Slot C, Chip 9, SDRAM U59: MAC:0x000012, bank 0, port 2 MSW, exp:0x739c actual:0x339c
Slot C, Chip 9, SDRAM U59: MAC:0x000015, bank 0, port 2 MSW, exp:0xce73 actual:0x8e73
Slot C, Chip 9, SDRAM U59: MAC:0x000016, bank 0, port 2 MSW, exp:0xe733 actual:0xa733
Slot C, Chip 9, SDRAM U59: MAC:0x000017, bank 0, port 2 MSW, exp:0x7339 actual:0x3339
Slot C, Chip 9, SDRAM U59: MAC:0x00001b, bank 0, port 2 MSW, exp:0xce73 actual:0x8e73
Slot C, Chip 9, SDRAM U59: MAC:0x00001c, bank 0, port 2 MSW, exp:0xe739 actual:0xa739
-- Reading Bonus Data --
> Slot C, Chip 9: Slave Clock from Chip 9 Test Failed!
-- Reading Full Channel Normal Data --
-- Reading Bonus Data --
Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
TEST 3: Master Clock from CHIP 8 thru Chip 9 ...
-- Reading Full Channel Normal Data --
Slot C, Chip 9, SDRAM U59: MAC:0x000000, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
Slot C, Chip 9, SDRAM U59: MAC:0x000002, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
Slot C, Chip 9, SDRAM U59: MAC:0x000003, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
Slot C, Chip 9, SDRAM U59: MAC:0x000005, bank 0, port 2 MSW, exp:0x6d9b actual:0x2d9b
Slot C, Chip 9, SDRAM U59: MAC:0x000006, bank 0, port 2 MSW, exp:0xd9b6 actual:0x99b6
Slot C, Chip 9, SDRAM U59: MAC:0x000009, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
Slot C, Chip 9, SDRAM U59: MAC:0x00000a, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
Slot C, Chip 9, SDRAM U59: MAC:0x00000d, bank 0, port 2 MSW, exp:0xdb66 actual:0x9b66
Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0x66db actual:0x26db
Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
Slot C, Chip 9, SDRAM U59: MAC:0x000011, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
Slot C, Chip 9, SDRAM U59: MAC:0x000013, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
Slot C, Chip 9, SDRAM U59: MAC:0x000014, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
Slot C, Chip 9, SDRAM U59: MAC:0x000016, bank 0, port 2 MSW, exp:0x6d9b actual:0x2d9b
Slot C, Chip 9, SDRAM U59: MAC:0x000017, bank 0, port 2 MSW, exp:0xd9b6 actual:0x99b6
Slot C, Chip 9, SDRAM U59: MAC:0x00001a, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
-- Reading Bonus Data --
> Slot C, Chip 9: Master Clock from Chip 8 thru Chip 9 Test Failed!
-- Reading Full Channel Normal Data --
-- Reading Bonus Data --
Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
TEST 4: Slave Clock from CHIP 8 thru Chip 9 ...
-- Reading Full Channel Normal Data --
Slot C, Chip 9, SDRAM U59: MAC:0x000002, bank 0, port 2 MSW, exp:0xc631 actual:0x8631
Slot C, Chip 9, SDRAM U59: MAC:0x000003, bank 0, port 2 MSW, exp:0x6318 actual:0x2318
Slot C, Chip 9, SDRAM U59: MAC:0x000007, bank 0, port 2 MSW, exp:0xcc63 actual:0x8c63
Slot C, Chip 9, SDRAM U59: MAC:0x000008, bank 0, port 2 MSW, exp:0xc631 actual:0x8631
Slot C, Chip 9, SDRAM U59: MAC:0x000009, bank 0, port 2 MSW, exp:0x6318 actual:0x2318
Slot C, Chip 9, SDRAM U59: MAC:0x00000d, bank 0, port 2 MSW, exp:0xc633 actual:0x8633
Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0x6331 actual:0x2331
Slot C, Chip 9, SDRAM U59: MAC:0x000013, bank 0, port 2 MSW, exp:0xc631 actual:0x8631
Slot C, Chip 9, SDRAM U59: MAC:0x000014, bank 0, port 2 MSW, exp:0x6318 actual:0x2318
Slot C, Chip 9, SDRAM U59: MAC:0x000018, bank 0, port 2 MSW, exp:0xcc63 actual:0x8c63
Slot C, Chip 9, SDRAM U59: MAC:0x000019, bank 0, port 2 MSW, exp:0xc631 actual:0x8631
Slot C, Chip 9, SDRAM U59: MAC:0x00001a, bank 0, port 2 MSW, exp:0x6318 actual:0x2318
Slot C, Chip 9, SDRAM U59: MAC:0x00001e, bank 0, port 2 MSW, exp:0xc633 actual:0x8633
Slot C, Chip 9, SDRAM U59: MAC:0x00001f, bank 0, port 2 MSW, exp:0x6331 actual:0x2331
Slot C, Chip 9, SDRAM U59: MAC:0x000024, bank 0, port 2 MSW, exp:0xc631 actual:0x8631
Slot C, Chip 9, SDRAM U59: MAC:0x000025, bank 0, port 2 MSW, exp:0x6318 actual:0x2318
Slot C, Chip 9, SDRAM U59: MAC:0x000029, bank 0, port 2 MSW, exp:0xcc63 actual:0x8c63
-- Reading Bonus Data --
> Slot C, Chip 9: Slave Clock from Chip 8 thru Chip 9 Test Failed!
-- Reading Full Channel Normal Data --
-- Reading Bonus Data --
Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
TEST 5: Psync Clock from CHIP 8 thru CHIP 9 ...
-- Reading Full Channel Normal Data --
Slot C, Chip 9, SDRAM U59: MAC:0x000001, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
Slot C, Chip 9, SDRAM U59: MAC:0x000002, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
Slot C, Chip 9, SDRAM U59: MAC:0x000004, bank 0, port 2 MSW, exp:0x6db7 actual:0x2db7
Slot C, Chip 9, SDRAM U59: MAC:0x000005, bank 0, port 2 MSW, exp:0xdb76 actual:0x9b76
Slot C, Chip 9, SDRAM U59: MAC:0x000007, bank 0, port 2 MSW, exp:0x76db actual:0x36db
Slot C, Chip 9, SDRAM U59: MAC:0x000008, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
Slot C, Chip 9, SDRAM U59: MAC:0x000009, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
Slot C, Chip 9, SDRAM U59: MAC:0x00000b, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
Slot C, Chip 9, SDRAM U59: MAC:0x00000c, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
Slot C, Chip 9, SDRAM U59: MAC:0x00000e, bank 0, port 2 MSW, exp:0x6ddb actual:0x2ddb
Slot C, Chip 9, SDRAM U59: MAC:0x00000f, bank 0, port 2 MSW, exp:0xddb6 actual:0x9db6
Slot C, Chip 9, SDRAM U59: MAC:0x000010, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
Slot C, Chip 9, SDRAM U59: MAC:0x000012, bank 0, port 2 MSW, exp:0x6db6 actual:0x2db6
Slot C, Chip 9, SDRAM U59: MAC:0x000013, bank 0, port 2 MSW, exp:0xdb6d actual:0x9b6d
Slot C, Chip 9, SDRAM U59: MAC:0x000015, bank 0, port 2 MSW, exp:0x6db7 actual:0x2db7
Slot C, Chip 9, SDRAM U59: MAC:0x000016, bank 0, port 2 MSW, exp:0xdb76 actual:0x9b76
Slot C, Chip 9, SDRAM U59: MAC:0x000018, bank 0, port 2 MSW, exp:0x76db actual:0x36db
-- Reading Bonus Data --
> Slot C, Chip 9: Slave Clock from Chip 9 thru Chip 8 Test Failed!
Slot C, Chip 9: Bad SDRAMs: U59 Bad Data: 0x4000
TEST 6: Master Clock from CHIP 8 ...
-- Reading Full Channel Normal Data --
-- Reading Bonus Data --
TEST 7: Slave Clock from CHIP 8 ...
-- Reading Full Channel Normal Data --
-- Reading Bonus Data --
TEST 8: Master Clock from CHIP 9 thru CHIP 8 ...
-- Reading Full Channel Normal Data --
-- Reading Bonus Data --
TEST 9: Slave Clock from CHIP 9 thru CHIP 8 ...
-- Reading Full Channel Normal Data --
-- Reading Bonus Data --
TEST 10: Psync Clock from CHIP 9 thru CHIP 8 ...
-- Reading Full Channel Normal Data --
-- Reading Bonus Data --
TEST 11: Poststore Counter Test ...
Mod C: TEST FAILED # "clksTest" (1, 1, -1)
Which leg did you lift? One of the data lines?
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=00000002, act=00000000
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFFE, act=FFFFFFFC
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFFB, act=FFFFFFF9
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFF7, act=FFFFFFF5
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFEF, act=FFFFFFED
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFDF, act=FFFFFFDD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFFBF, act=FFFFFFBD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFF7F, act=FFFFFF7D
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFEFF, act=FFFFFEFD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFDFF, act=FFFFFDFD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFFBFF, act=FFFFFBFD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFF7FF, act=FFFFF7FD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFEFFF, act=FFFFEFFD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFDFFF, act=FFFFDFFD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFFBFFF, act=FFFFBFFD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFF7FFF, act=FFFF7FFD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFEFFFF, act=FFFEFFFD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFDFFFF, act=FFFDFFFD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFFBFFFF, act=FFFBFFFD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFF7FFFF, act=FFF7FFFD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFEFFFFF, act=FFEFFFFD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFDFFFFF, act=FFDFFFFD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FFBFFFFF, act=FFBFFFFD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FF7FFFFF, act=FF7FFFFD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FEFFFFFF, act=FEFFFFFD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FDFFFFFF, act=FDFFFFFD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=FBFFFFFF, act=FBFFFFFD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=F7FFFFFF, act=F7FFFFFD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=EFFFFFFF, act=EFFFFFFD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=DFFFFFFF, act=DFFFFFFD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=BFFFFFFF, act=BFFFFFFD
Slot A, Analysis Chip Data Bit Failed, chip 9, port 2, exp=7FFFFFFF, act=7FFFFFFD
Slot A, Analysis Chip Data Bit Error, chip 9, port 2, bits=00000002
Mod A: TEST FAILED # "anlyBusTest" (3, 3, -1)
I have locate a single trace, that was broken between the acqusition ASIC and the FPGA glue logic that damn f...failed trace was hidden UNDER OVERLAY, uh. It was looking kinda clocky, as it was length matched.
Now I see the following result of anlyBusTest:
...