"NU180" - A U180 drop-in replacement for the 3458A.

[MiDi]

Changing A3 / U180, ACAL DC should be sufficient.
For measuring absolute INL, CAL 0 and CAL 10 are required.
For relative INL, offset and gain can be corrected afterwards, e.g. with least squares.

Based on my preliminary understanding of the 3458A's quantization process, to obtain a relatively accurate DCV value, at least the following need to be known: the ratio between +ref and -ref, and the ratios（direct or relative） of S256, S64, S16, S4, and S1 (in the switching network) to one of the reference voltages. These should be the so-called calibration parameters. In which process are these calibration parameters obtained and recorded—during ACAL or CAL operations?

There are no CAL constants for the RN ratios, so it looks like it relies on the RN abs. ratio & ratio stability.
The ratios for scale to the refs are corrected by CAL 10V to some degree.

[Kleinstein]

The ratios of +- ref, S64,S16,S4,S1 are set by the resistors. AFAIK the 3458 relies on accurate resistors here and uses nominal values. The ladder part and the related 5 V ref. has an only limited influence. With 1 PLC conversions the DNL may be a bit limited be the resistor values, especially the symmetry in the positive an negative references. The influence is still not super large, via the S256 run-down part.
With 10 PLC the rundown part is small enough, so that the resistor accuracy is no longer that critical.
The rather fast RU modulation helps to keep the run-down part not so important.

The absolute scale factor is adjusted relative to the reference voltage in ACAL DCV.
The CAL 0 part should be mainly for the front end (especiall therma EMF) and thus not effected by changes to the A3 board. One may need a good value here to do turn over tests.

[wanghar]

There are no CAL constants for the RN ratios, so it looks like it relies on the RN abs. ratio & ratio stability.
The ratios for scale to the refs are corrected by CAL 10V to some degree.

HPAK has sufficiently good RN (inside U180), so relying on its high accuracy and ratio stability, a relatively simple calibration method could indeed be used. This does make sense.

The ratios of +- ref, S64,S16,S4,S1 are set by the resistors. AFAIK the 3458 relies on accurate resistors here and uses nominal values. The ladder part and the related 5 V ref. has an only limited influence. With 1 PLC conversions the DNL may be a bit limited be the resistor values, especially the symmetry in the positive an negative references. The influence is still not super large, via the S256 run-down part.
With 10 PLC the rundown part is small enough, so that the resistor accuracy is no longer that critical.
The rather fast RU modulation helps to keep the run-down part not so important.

The absolute scale factor is adjusted relative to the reference voltage in ACAL DCV.

Using the ratios of resistors as calibration factor might pose a challenge for NU180. The ratios for the minor slope section during rundown may not be a major issue, but since the consistency of the four 80K resistors is unlikely to reach a very high level (as U180), this might introduce INL or gain error during the runup phase.  Could the noticeable gain error observed in the 0V to -10V range also be related to this?

[DB4UCH]

Using the ratios of resistors as calibration factor might pose a challenge for NU180. The ratios for the minor slope section during rundown may not be a major issue, but since the consistency of the four 80K resistors is unlikely to reach a very high level (as U180), this might introduce INL or gain error during the runup phase.  Could the noticeable gain error observed in the 0V to -10V range also be related to this?

The problem aren't the 80ks as per the HP journal the ratio stability just needs to be ~3%, which is easy the problem are the 20ks which need way better matching. (0.1%)

I have my V0.4 board up and running. It sadly isn’t stable at all. (Slow mode is ok, fast mode not really) If I trim the 5V reference it's stable, but missing at least the S1 / S4 slopes, therefore massively reducing the resolution. (In this state it actually passes self-test and ACAL DCV.) I think this is related to timing; I will have to experiment more. Preliminary noise measurements show a ~30% improvement at 1 NPLC, now ~0.10PPM of range. (Short, 10V range) INL seems worse. (Better than +-1PPM tho)

Greetings,
Simon

[Kleinstein]

The 20 K resistors only matter for the very fast mode. This part has a less accurate amplifier and the external 10 K resistor. It is thus never expected to get very good INL. In addition with the nu180 the switch resistance is not in the same ratio as for the 80 K and others.
The 80 K resistors should still be quite a bit better than 1%. This would not be much for the run-up, as there are used in pairs there with only one scale factors from the difference of the +-12 V references and the average of all 4 80 K resistors. The Run-up steps use either the positive side or the negative side and thus only the difference matters. A mismatch would not effect the positive / negative readings separate.

The positive to negative side matching in the +- ref. and the 80 K resistors is relevant for the S256 run-down part. Worst case this would be close to 2 of the run-up steps compared to some 6000 run-up steps at 1 PLC. To get 0.1 ppm range DNL this would require a matching of some 300 ppm = 0.03%. So this are pretty tight specs that would be wanted. Here it helps a little to have 2x80 K effectively in parallel compared to another pair and thus some statistical avereraging that helps a little. If really needed one could consider to trim one of the 80 K resistors. This would also cover the +-12 V ref. step - they all come togehter to one effective cal constant.
The linearity specs are for 10 PLC and longer, where the resistor tolerances are less critical by the factor of 10.

The 3% number is more the accuracy level needed for the ladder part on the A3 PCB.

[Zondar]

I have my V0.4 board up and running. It sadly isn’t stable at all.

I have mine installed too. It is not working, and delivers a hardware 202 error, "slave test: convergence," after which no operation proceeds.

I presume you are using the rising edge? Have you tried the falling one? Neither works for me, with both producing the same error. The clock inverter, 3.3V regulation and 3.3V FF's do work fine. The CPLD and FF outputs produce signals, but they stop completely once the error occurs.

[DB4UCH]

I firstly ran the board with the inverter not populated. (I just bridged the 20 MHz clk to the FFs and the CPLD) Without any modifications it passed the power on self-test but didn't run reliably at all.
I have now installed an inverter and it seems to run better now. (Not 100% tho, still throwing 114s every now and then but ACAL DCV works now (OHMS doesn't)) (I have connected the CPLD and FFs both to the inverter output rn. & currently fast mode is also enabled at the CPLD, but I don't know if that’s related)

For your startup issue I would recommend you double and triple check all your solder joints at the switches and control signals for the slopes + the resistors and ref voltages. With my previous PCBs a startup issue was nearly always located there. The PCB and the CPLD code works.

Greetings,
Simon

[wanghar]

I have now installed an inverter and it seems to run better now. (Not 100% tho, still throwing 114s every now and then but ACAL DCV works now (OHMS doesn't)) (I have connected the CPLD and FFs both to the inverter output rn. & currently fast mode is also enabled at the CPLD, but I don't know if that’s related)

On your V04 board, there’s a voltage selection jumper. Have you observed different results with different voltage settings?

I finished soldering my board with an external flip-flop chip yesterday and tested it on the A3 board—the results matched expectations. The flip-flop chip I used is the 74AHC273, with the clock signal routed through a 74LVC1G14 before reaching the flip-flop. The rest of the design doesn’t differ much from yours and Zondor's.

For power: the CPLD, flip-flop, and two ADG734 chips are all powered by 5V. The two ADG734 chips controlling +ref and -ref are supplied by VDD2. The board doesn’t use trim resistors, and I haven’t encountered error codes 114 or 202 so far.

Noise performance is acceptable (shorted, 10V range, rms):

1PLC: 0.86 µV

10PLC: 0.35 µV

the measured temperature coefficient is about 1.8 ppm/°C.

INL is ≤0.3 ppm across the range of -10V to +10V. As for INL, I’m inclined to think that with the current hardware (four discrete 80K 0.1% resistors), it might be hard to break through this level.

[DB4UCH]

I've now gotten my v0.4 stable enough. (I'm still not trusting the fast mode fully, but it now passes ACAL DCV and OHMS reliably). (I've set the CPLD to trigger on falling flanks and fast mode is enabled, the FFs need to also be inverted and running on 5V, otherwise it’s not stable. I also have installed 20pF at the slope amp.) I have a different inverter with a lower propagation delay that I want to try as well.

But now for some measurements:

INL shows some gain error. This error is not dependent on any sort of V_OH issue, as enabling pin keep at the CPLD or installing pulldowns at the series resistors show no change in this behavior. The gain error is therefore of a different origin.
The plot shows some noise that is most likely created by temperature variation and the 34401As.
I tried to swap the switch configuration from one switch IC per reference voltage to a more distributed approach (like on MiDis boards (one 80k & 20k per +-ref per IC), but the board with this modification wasn't able to start successfully, of course I changed the CPLD code as well )

For noise: The 0.1PPM of range figure has stayed constant throughout my testing.

The different zero-point dependent on NPLC seems to exist here as well, but it is limited in amplitude to <0.3µV. i.e not that critical.

Generally speaking, I think that we have some very tight timing requirements to get proper stable operation.

Greetings,
Simon

[Zondar]

It seems each machine is slightly different and requires different tweaks to achieve operation.

I'm still struggling with my board. I did find a microscopic short between two switch pins, after which the 202 hardware error changed to a 114 error ("system error; balanced rundown convergence"). It still won't operate at all, though. At present, I have 3.3V FF's running off an inverted clock. The CPLD is as in Simon's posted code, and I haven't tried reprogramming it yet.

Simon, you say it did not work for you unless a 5V FF was used? Your current configuration is 5V FF's and falling edge for both FF's and CPLD? What value series resistors have you used? What else specifically was necessary to get it to run?

Thanks.

[DB4UCH]

Zondar, that’s progress at least!
The FF I use is a CD74HCT574PWR (5V type needs to run at 5V to be stable). The inverter I used at the beginning for my (mostly stable board) is a 74AHC1GU04GW,125.  [I know I didn't pick the best parts lol.] My series resistors are all 100 Ohms.
I use falling edge for both FFs and CPLD. One can then also invert the clock in the CPLD. This could lead to slightly more stable performance. (But you aren't at that point yet (most likely).)
Those were the steps I needed to get a mostly stable board.

You might also try to put your finger on the control resistors to see if some tweaking is required.
If you have some capacitor installed at the slope amp, maybe try to remove this, too. (For me this was the only time where I saw this balanced error variant appear commonly)

Other than this I'm kind of out of ideas.

Greetings,
Simon
P.S. I think I have found the origin of the remaining gain error and it should be fixable by a slight design change, more to follow, I will investigate more. And this has nothing to do with V_OH.
Edit: I'm not fully sure that what I think of, is actually the solution, we still might want to try it.

[Zondar]

For the inverter, I used a 74LVC1GU04 (running at 5V), and for the flip-flops, a 74LVTH574 (running at 3.3V, with 5V tolerant inputs). Both of these are fairly fast. I ran out of 100 Ohm series resistors, so I went back to 33 Ohms. I subsequently tried 220 Ohms on the S11 switch, which helped on one of my older boards, but it did not help this time. On your advice, I removed 10 pF from R140, which also did not help.

I have a 5V flip-flop available to swap in if necessary, though I would not expect that using 3.3V logic to the switches would be the problem.

It appears that your posted CPLD code uses the clock input straight, without an additional inversion. Therefore, the 5 outputs latched by the CPLD should still latch on the falling edge of U180's clock, as before. I don't see a reason to change this unless the flip-flops also successfully use the rising edge.

One potential reason to pursue using 3.3V logic to the switches is that it would allow using VDD2 (~4.4V) to power the switches, as the real U180 effectively does, instead of VDD1 (5V). That technically wouldn't be within spec if 5V logic is used (wanghar take note of this*), but it would be fine if 3.3V (or ~4V using pull-downs) is used. The point is that VDD2 may be quieter, since it's not used by the CPLD, etc., while it's still high enough for low R_ON and good linearity around 0V.

* I can look at this again to be sure, but I recall that the ADG's did not like having inputs go more than ~0.3V above Vdd. The problem is that the inputs themselves will start to power the chip instead of Vdd, which is not good at all. At ~4.4V it's a close call and may work, though.

[DB4UCH]

P.S. I think I have found the origin of the remaining gain error and it should be fixable by a slight design change, more to follow, I will investigate more. And this has nothing to do with V_OH.
Edit: I'm not fully sure that what I think of, is actually the solution, we still might want to try it.

About this:

I already mentioned that I tried to change the reference voltage configuration at the switches on this new board. (i.e. one 80k and 20k per reference rail per switch and not a dedicated switch IC per rail)
This is the only systematic difference between MiDis design and the other two families of designs. And with MiDis board I was able to basically eliminate any sort of gain error.

I managed to get the unit to startup by changing the series resistors and was therefore able to get it to run somewhat stable. I investigated the gain error in this state using the front rear switch to switch the polarity around and found a gain error <0.2PPM. (My unmodified unit has ~1.5PPM of gain error)
I don't trust the measurement 100%, so I don't know if that is the solution, but I think it's worth a try.

I therefore propose that we might want to try this on a new revision. (The different distribution of ref voltages to the switches as per MiDis design. (Schematic attached below for reference)

Greetings,
Simon

Edit: Now my (returned to previous condition) board shows incresased noise, so I think I might have damaged something during my experiments...

[Zondar]

Is it only the arrangement of the switches that is different, i.e. instead of one package on +12V and one on -12, you have both + and - per package? If so, why do you think that helps?

What did you change about the series resistors?

Is it clear that the use of external FF's has helped?

I am fine with another board iteration if solutions to problems can be achieved, and have a few changes in mind too (e.g. 805 series resistors, effort to move bottom caps to top, improved clock distribution, change switches to VDD2, and so on).

What's missing? I wish the quirky stability issue could be definitively solved.

[wanghar]

Is it clear that the use of external FF's has helped?

I am fine with another board iteration if solutions to problems can be achieved, and have a few changes in mind too (e.g. 805 series resistors, effort to move bottom caps to top, improved clock distribution, change switches to VDD2, and so on).

Using an external flip-flop (FF) is effective. Another test I did on this PCB (see photo): I removed the FF chip and bridged the original FF pads with solder joints to create a direct connection. Without pull-down resistors, there was a gain error of about 2 ppm. After adding four pull-down resistors, the INL caused by gain error dropped to around 0.3 ppm. This means both pull-down resistors and an external FF can eliminate the gain error and INL issues caused by V_OH, but we may prefer using an FF chip.

About VDD2. On my PCB, it’s also selectable to power U1 and U2 with 5V, but I noticed occasional 114 errors when using 5V. After switching to VDD2, I never encountered this error again—and this behavior was confirmed on the 2nd PCB. The ADG734 datasheet does mention that Vin should be less than VDD + 0.3V, but so far, no issues have appeared in actual use. For a safer approach, you could place a 15Ω resistor at R118. This would lower the voltage for both the CPLD and the FF to around 4.70V. I’ve tried both a 15Ω resistor and a 0603 ferrite bead, resulting in voltages of 4.70V and 4.99V respectively, with no noticeable difference in performance.

Overall, this version of the PCB shows improvements in noise, stability, and INL compared to previous versions, though temperature drift related to the resistors remains similar to before.

[Zondar]

Overall, this version of the PCB shows improvements in noise, stability, and INL compared to previous versions, though temperature drift related to the resistors remains similar to before.

OK, it's great to hear confirmations like this!

The reason I originally went with VDD1 instead of VDD2 is the switch power supply vs. input signal voltage limitation. I did test this to confirm that the problem is real using my little ADG test board. You may not see much impact on these boards in practice, and the stress may not be enough to break the chips, but it's definitely a thing.

It's good to hear proof that using VDD2 shows benefits, and we should adopt that. To facilitate this, unless it's demonstrated that using 3.3V FF's is somehow worse than the ~4V using pull-downs (it shouldn't be), then I'd recommend going with 3.3V. Newer 3.3V chips are often faster than old-school 5V ones anyway, and the regulator should provide decent noise rejection and isolation too (those FF's are high transient current parts).

You also seem to say that pull-downs and external FF's result in similar amounts of INL improvement. Regardless, I'd agree that the external FF's, at 3.3V anyway, should be better. For one, it eliminates the quite bad ~1 mA of current used by each pull-down when logic-high.

I note that you say the resistors still results in noticeable temperature-related drift. On the other hand, Simon's results seem to be fine. (But how 5 or 10 ppm resistors, even doubled up, etc., could result in 0.1 ppm temp stability is curious to me.)

I'm still wondering how (I think) merely re-arranging the switches, per MiDi's design, could result in the significant improvements that Simon suggests are available there. But it would be good if it holds up, of course.

If my V0.4 board design remains a good platform for improvements, then I'm happy to implement whatever changes are agreed on. Probably a little more investigation on some of these topics should take place first, though.

Finally, my board still doesn't work, but I haven't had a chance to look at it recently. You guys are better and faster at these tests and measurements than I am anyway, so proceed!

Edit: I guess I should join in and post an image of my board too. 

[Kleinstein]

There could be multiple reasons for the different gain for the positive and negative direction: one could be interference back to the 5 V supply, that seems to come directly from the oscillator supply. I had that type of issue with my early AVR based system.
Another similar point could be capacitive coupling from the clock signal to a ref. control signal (especially from the CPLD). The output impedance of the outputs, especially without pull down is higher in high state than in low state. This gives a different amount of effective capacitive loading and delay.
The design when all the way of using extra vias to shield the clock input.
Another possible issue could be local supply ripple effecting the FF or switches. The number of double short pulses about scales with abs(U) and thus can effect the ripple for the later switching events in the 2nd pulse.

Which switches are shared on chip effects the layout / parasitics. It also effects the interaction from multiple switches operating togehter. AFAIK there are usually 4 switches operated at the same time. At the few ns range the switches on a chip interact somewhat, no matter how good the supply decoupling.

The reported temperature drift is at some 1-2 ppm/K for the cheaper resistors (e.g. 5 or 10 ppm class). This is plausible with a moderate temperature range and resistors from the same series or even same reel. It is no guaranteed, but resistors tend to be better at moderate temperature and still have some matching (e.g. similar 2nd order part from same material).

[iMo]

..perhaps you may try to simulate the critical parts/paths in the LTspice.. The ADG734 switches are there in the lib and you may play with ps/pF/ohms/voltages, etc. to get the better picture..

[Zondar]

I wonder how accurate their models would be. Spice parameter decks for semiconductor fab lines are normally considered proprietary and not handed out without confidentiality agreements. Similarly, circuit schematics and parameters such as transistor W/L's are not normally made available for commercial parts. Without all that, simplistic switch functionality could presumably be modeled, but nothing much fancier.

It's not available for linux (why!?) or I'd give it a try, but there's no way I'd put up with using windows for that.

[DB4UCH]

I note that you say the resistors still results in noticeable temperature-related drift. On the other hand, Simon's results seem to be fine. (But how 5 or 10 ppm resistors, even doubled up, etc., could result in 0.1 ppm temp stability is curious to me.)

That 0.1 PPM figure is the noise, you are right that a TC of 0.1PPM/K is hard to imagine. It's more in the range of 1-3PPM/K

You also seem to say that pull-downs and external FF's result in similar amounts of INL improvement. Regardless, I'd agree that the external FF's, at 3.3V anyway, should be better. For one, it eliminates the quite bad ~1 mA of current used by each pull-down when logic-high.

The fact that pulldowns and the external FF show the same sort of improvement is not terribly surprising, as both fix the V_OH issue on a basic level, which was the major contributor to the gain error. I think the experiment wanghar did shows that both ways to fix this issue are equally usable and that this issue is therefore fixed. I am definitely still in favor of using FFs, as they not only fix the V_OH issue, but also reduce the noise. (like Kleinstein predicted, mine and wanghars (I think, but the impact in wanghars case was smaller) results showed this)

As for shifting the references around: The reason I want to try this is that, with MiDis board, the gain error is completely removed (i.e. the difference is in the INL spec) after installing the pulldowns. This worked on two PCBs. This might, of course, be a different mechanism at play, but with one switch IC per reference, (for the slow mode) you have two switches that get closed or opened at once, while with the shifted references you have only one switch that opens and one that closes per IC. Because such small effects are kind of hard to investigate on their own, I think we just need to try this on a different PCB.

I am willing to design and build an intermediate version of the V0.4 PCB that only tests the different switch configuration and different a power source for those. (i.e. 5V vs VDD2 switchable)

I would also like to try a 3.3V FF, does anyone have any recommendation for a specific part?

..perhaps you may try to simulate the critical parts/paths in the LTspice.. The ADG734 switches are there in the lib and you may play with ps/pF/ohms/voltages, etc. to get the better picture..

I did play around with LTSpice for a bit, the data can be found here: https://www.eevblog.com/forum/metrology/nu180-a-u180-drop-in-project-for-the-3468a-dvm/msg6106171/#msg6106171
Although I don't know if we can really learn much here.

It's not available for linux (why!?) or I'd give it a try, but there's no way I'd put up with using windows for that.

Afaik it runs well under Wine.

Greetings,
Simon

[Zondar]

From a post I made above:

"For the inverter, I used a 74LVC1GU04 (running at 5V), and for the flip-flops, a 74LVTH574 (running at 3.3V, with 5V tolerant inputs). Both of these are fairly fast."

Perhaps MiDi can respond with his reasoning for his switch configuration? But if it works, it works, and I'll be glad to hear confirmation.

[Barry Ward]

Wanghar and all,

While I still am not ready to run a board or temperature tests, I cringe when I see resistors that you expect any tempco performance from - applied to a board without attention to the physics.   I've tested quite a few different resistors and values in my quest to get my homebrew laser trimmer going.   

Even space qualified TaN (which are extremely stable) vary depending on the force applied during soldering and afterward in the application.

I'd try standing the critical ratio resistors on end and running some small wire from the top to the board (or at least slotting around one terminal).  It should be "easy" if you have a running board that you have already collect some data from.

People go nuts with the slots around their references, give your poor lowly resistors some love.

There are a lot of variables in getting this project to work and I have tremendous respect for all of you and your diligence.  Thank you all !

[MiDi]

The reason for the interdigitized switch arrangement was simply to get a better balance/cancellation between + and - slopes with no downsides and easy to implement - but would not overestimate the effect.

Regarding V_OH thing, the datasheet for the CPLD shows that there is essentially zero source current capability over 4V (see attachment & DS p. 22).
If using VDD2 (~4.4V) the pin keeper should be disabled, iirc zondar measured only up to 4V in this mode, so this seems to be no problem.

Code: [Select]

PROPERTY ATMEL { PIN_KEEP = OFF };          /* all outputs w/o pin keeper      */
With pull-downs at the outputs of the CPLD (or are they at the input of the switches?) in conjunction with series resistance and input capacitance it effectively delays the switching and reduces slew-rate (improving jitter?).
AFAIR there was no difference for fast mode on/off w/o pull-downs, which should have similar effect.

Code: [Select]

PROPERTY ATMEL { OUTPUT_FAST = ON };        /* all outputs use fast slew rate  */

TBH it is hard to follow the changes and the corresponding effects over 27 pages - would help if there would be schematics with the used component values (or put a link if it was already posted) and e.g. some scope screenshots before/after in those posts.

"What you can't measure, you can't improve"

[Zondar]

Yes, if pin-keeper is off (and no pull-downs), the pull-up transistors will cease providing current at somewhere around 4V, since the pull-up output transistor - which is N-channel, hence with a large Vt due to the body effect - will fall below threshold. It will maintain that value, though, since if it sags down, the transistors will start to conduct again. On the other hand, if it drifts up somehow, for example due to pin-keeper, the output transistor will still not conduct. Pull-downs cause the transistor to stay on, at least a little above threshold, and hence the output will rise and stabilize quickly.

When using pull-downs, it's best if pin-keeper is off. However, pin-keeper acts through a 100k resistor, so when using 5k pull-downs, even if it's on, there shouldn't be much trouble in practice.

In my experience, it's generally the case that faster slew rates will result in lower jitter. It's easy to see why, since if you lower the slew rate to an absurd degree, the dv/dt becomes so low that noise will come to dominate the threshold crossing.

I agree that 27 pages is a lot, and that info tends to get hard to find by now. In the first post, I put the KiCad files for V.0.4, zipped, at the bottom. That's something, at least. Note that some of the minor parts such as caps and series resistors include some stand-in values that may still differ from board to board based on parts availability or individual choice. Simon's version is based on the same but is slightly different. Wanghar's latest has some of the same features but probably deviates more.

[wanghar]

While I still am not ready to run a board or temperature tests, I cringe when I see resistors that you expect any tempco performance from - applied to a board without attention to the physics.   I've tested quite a few different resistors and values in my quest to get my homebrew laser trimmer going.   

Even space qualified TaN (which are extremely stable) vary depending on the force applied during soldering and afterward in the application.

I'd try standing the critical ratio resistors on end and running some small wire from the top to the board (or at least slotting around one terminal).  It should be "easy" if you have a running board that you have already collect some data from.

People go nuts with the slots around their references, give your poor lowly resistors some love.

There are a lot of variables in getting this project to work and I have tremendous respect for all of you and your diligence.  Thank you all !

I think we’re probably getting close to the point where we’ll need to discuss the selection and proper utilization of precision resistors. Right now, we still focus on verifying and solidifying some of the basic checkpoints first.