"NU180" - A U180 drop-in replacement for the 3458A.

[wanghar]

Critical error fixed in A3 replica

Thanks MiDi! Bringing the 7 control signals going into U180 out to a SIP connector is an good idea as shown in the new release. That  really makes it convenient to capture those waveforms and timing with a scope.

[DB4UCH]

An update about my v0.4.3 sub revision:
It’s kind of a failure...
The U180 doesn’t pass the power on self-test, swapping it in after having passed the power on self-test shows that the slow mode works, but the fast mode not at all. Changing around the clock config etc. doesn’t change this, the slopes also look good, so I don't know where the problem lies.

About the slow mode: Noise is way worse at about 0.15PPM of Range at 1NPLC, 10V range (the v0.4.2 has a noise 0.1PPM of Range here)
But the worse thing: I get a gain error of >200PMM that isn't timing related. Also swapping around the switches / even the references doesn't change this behavior Also Gate modulation etc. shows no improvement here (not surprising as the sort of error to be corrected by the gate modulation is way smaller than 200PPM).

I will play around some more, but I think that changing the switches isn't the way to go.

Greetings,
Simon

P.S. About this:

I will now try to bridge the FFs on my v0.4.21 PCB to see if I can fix it the same way I think I was able to do it on MiDis first revision or to see if this was a fluke.

Bridging the FF I can report two things:
1. The difference in Zero point can be reduced this way (<100nV difference between 10 and 100NPLCs ~300nV difference between 10 and 1NPLC vs. ~800nV to 1µV difference)
2. The FFs don't seem to do much for noise, as the noise remains unchanged between FFs and bridges. As wanghar uses a different type of FFs, he might see more improvement, explaining his slight advantage in noise.

[Zondar]

It's wonderful to see more and more people experimenting and trying new ideas to improve performance!

I think my own next step is to maintain a "baseline" version that others can rely on as a starting point. This would be much like my V0.4 plus Simon's V0.4.1 improvements, plus with a few other changes based on people's findings.

I communicated with Simon, who helpfully made a summary of the various things people have tried, along with his estimation of where those trials stand. Here's a condensed list along with suggested responses:

* Slope FF's: Improved linearity, but may have made the "zero issue" worse (how?). Still, it seems important to keep. Stays.

* Other FF's: No change, no reason to include. Delete.

* GND2 usage: GND2 is approximately -0.6V, providing some negative headroom, as U180 does, which is a good benefit. Continue to use GND2.

* VDD2 usage: VDD2 is about 4.4V, and can be used for the switch VDD under the assumption that it may be quieter than VDD1. However, people have reported no improvement with it. Also, the on-resistance would go up very slightly (~0.1 Ohm) if 4.4V is used. Use VDD2 (4.4V) if FF's use 3.3V.¹

* FF's at 3.3V vs. 5V: No improvement. Use 3.3V if switches use 4.4V via VDD2.¹

* AGND3 usage: Combining AGND3 with AGND1 and 2 increased noise. Note that AGND1 and 2 have an inductor between them and ground, whereas AGND3 does not. Keep AGND3 separate, as is.

* Clock inverter: Alternates like buffered or non-inverted clock either did not work, made no difference, or made things worse. Stays as is.

* ADG's vs. 4053's vs. TMUX switches: ADG's found to be superior to 4053's. I made an effort to try TMUX's as an alternate, but was unsuccessful in getting them to run (weak effort, should try again, but they are only marginally different from the ADG's anyway). Stick with ADG's.

* Gate modulation: Made no difference with the use of ADG's, made some difference with 4053's, but 4053's were found to be a bad choice. Some may wish it to stay anyway, and it's only a minor bit of circuitry, but I'm not seeing an advantage. My own view is that what people are using for "gate modulation" is not at all what the real U180 does, so I'd leave it out. No gate modulation(?).

* Series resistors: Differing values made little or no difference, and it's trivial to choose a different value anyway. Use 100 Ohms.² 

* Switch arrangement: MiDi's approach appears to yield a small benefit. Use MiDi's arrangement.

* Resistor arrays: Various trials, some successful, others less so. For a "baseline" board, I'd propose using four resistors per 80k and four for the 50k, in a parallel-series-parallel fashion like the real U180 uses for the 50k resistor. It's not clear to me if any others need this. Use 4 per 80k and 50k.

* FF choices: People have tried a few different FF's. I used 574's, but Kleinstein suggested one lacking tri-state outputs under the assumption that it may have less jitter. My opinion is that the FF (and inverter) should primarily be chosen based on speed, and other details are less important. No direct comparisons have been made as far as I know, so it's unclear whether there's any benefit to be had with one vs. another. Keep 574's(?)

¹ There is a technical spec issue with switch voltages: Running the switches at -0.6V to 5V slightly exceeds their voltage limits. Running them at -0.6V to 4.4V is safer, but then the control signals should be kept below 5V, or the control input voltage would also slightly exceed specs (also the on-resistance would grow by ~0.1 Ohm). Technically, the safest would be to run the FF's at 3.3V and the switches on VDD2 (4.4V). However, people have been running everything at 5V without any reported problems, and the excess voltage is only ~0.1V anyway. Though I noted choices above, I haven't firmly decided which approach to use. Opinions?

² Changes to some series resistors have sometimes helped, I believe by changing the skew between signals. I've long harbored a suspicion that the skew between switch control signals is responsible for some of the difficulty people have getting boards to run, or that it may contribute to linearity or zero issues, etc. In particular, the switch's turn-on and turn-off times are significantly different, like by 10ns or so. This means that, if one is turned on and another off "simultaneously," (does this happen?) there could or would be ~10 ns overlap between the two, which does not sound good at all. If the signals are produced by the CPLD, it's likely possible to mitigate some of this skew without too much trouble. But when using external FF's, that task becomes more difficult. I'm not sure what to propose about this - probably a little more investigation is needed. If there is no possibility of overlap or similar timing issues, then maybe it's OK.

Any differing experiences or opinions? Anything left out? Other suggestions?

Thank you.

[Kleinstein]

From the function a xx273 FF (common reset instead of OE) may have a slight advantage, but the xx574 FF ( with OE) has the much more convenient pinout with inputs on one side and the outputs at the other.

The gate modulation is needed with switches that have a higher on resistance. This could already be the case with LV4053 switches, but with 2 switches in parallel for the 50 K input the resistance can already be low enough.
The ADG834 or similar switch should no need the gate modulation and can be better of without.

Resistor arrays are a bit tricky as 80 K is not a standard value, and getting the 50 K from the same array is also tricky. This would really limit the choices.
A resistor array (LT5400) for the 10K/10 K inverter step seems to work well.
Similar the 7 to 12 V step may work with a resistor array.
The resistor choice can make quite some difference in the layout.


The series resistors in the control signals can effect the timing a little. In most cases the difference would be small and inside the break before make time. If the effectively parallel switches (like the pairs of 80 K channels) are "overlapping" there can be issues with the charge spike from the charge injection and some charge stored at the disconnected switch part. So I would aim for rather equal timing.
Switching at the same times seems to happen regularly - could well be 4 switches.

[Zondar]

FF's: Yes, I chose a fast 574 because of the better pinout. Many older IC's have awkward pinouts, I believe because only one metal layer was available at the time. That required prioritizing layout over pinout to avoid the use of higher-resistance polysilicon or diffusion jumpers.

Gate modulation: In the genuine U180, this is an analog function. The way people are using it on these boards appears substantially digital in nature. Maybe that still makes sense, but I don't understand it. Perhaps someone can clear that up? Anyway, it doesn't appear necessary in these boards with the ADG's.

Resistor arrays: I'd rather not go down the specialized resistor array rabbit hole again (so much discussion about that in the past!) unless there is proof of its value, and I haven't seen good evidence of that working out yet. Someone should please correct me if that's wrong.

As Kleinstein noted, getting good 80k's is particularly important yet annoyingly difficult. My own preferred solution is to order custom 80k (and 50k) metal foil resistors. I note that Wanghar used custom (leaded) metal foil's for the 80k's too, with good results. The 80k's cost me $25 each, which I feel is worthwhile (presuming it helps) given that even a broken 3458A can sell for many thousands.

That said, I don't want to force people down that path, so I was thinking the 4x parallel-series-parallel approach, or similar, with more ordinary resistors might be enough to help. I believe some people have already tried small arrays like that on their boards with reasonable outcomes. Coincidentally, the 4x resistors takes up the same amount of room as the very large 80k foil resistors need. That makes it easy to offer both options.

About skew: It is difficult to figure out a convenient way to independently control the skew between rising and falling edges. To start, I think I'll take a look at my little ADG test board again, and see if I can measure any overlap, etc.

[Kleinstein]

For the use of standard resistor arrays for the 80 K, one would need to combine quite some resistors:
80 K could be 4 x 20 K in series and thus 16 x 20 K
for the 50 K input resistor one could use 5 in series of 2 x 20 K in parallel = 10 resistors
            or                                           2 x 20 K in series + 2 x 20 K in parallel = 4 resistors.
One could split the resistors over 2 arrays equally, so that matching between the 2 arrays is not that critical.
So this would be 2 x 10 resistors (e.g. OSOP).
Another point could be getting the fast part to match. That could be another 4 x 20 K, from the same arrays. And thus 2 x 12 resistors as OSOP.
A slight issue is the switch resistance, that would add a little more for the 20 K, likely still OK, though not ideal !

[Zondar]

I think MiDi has tried some large arrays like that, but found that the capacitance grew high enough to be a problem. There was also an attempt using an LT5400, but this apparently made the TCR worse, possibly due to miss-matches with other resistors (TCR matching within one array is excellent, but they have very poor absolute TCR).

I spent many, many hours looking at just about every resistor array available, arranging them in many ways, and concluded that none look better - and most are worse - than simply using high-performance individual resistors, such as the metal foil ones I bought, and which Wanghar used.

Specialized arrays may still prove to be a good solution, but I'd like to hear more definitive comments about any successes and especially any comparisons that have been made.

[wanghar]

In terms of PCB revisions, I've made about 7–8 versions of the NU180 so far. One reason is that PCB fabrication is really convenient here – from sending out the design to receiving the boards, it takes as little as 5 days and at most 7 days. Quite often, when I have a new idea, I just spin a PCB version to try it out. Let me briefly share my thoughts from these testings.

The main topic of this thread is a drop‑in replacement for the U180. In that case, the four 80k precision resistors are a must. How to ensure good temperature coefficient tracking among those four 80k resistors is an unavoidable problem. Resistor arrays have naturally excellent TCR characteristics, but the unusual 80k value limits their use – there is currently no commercial 80k (or 40k) resistor array available. Using 20k arrays to combine into 80k introduces parasitic parameters that prevent the NU180 from working properly (MiDi's design confirmed this). At present, custom metal foil resistors seem a viable solution. Although custom resistors are not cheap, the cost is still acceptable (based on Zondar's USD $25/ea). My design uses leaded metal foil resistors with a 3.81mm (150mil) pitch (like the S102 series). In fact, such resistors also need to be custom ordered – they are never in stock on major distributor websites, and they are not cheap either. The reason I use them is that I often see 80k S102C pull‑outs on Taobao and Xianyu, at around USD $1‑2 each. I buy a batch of dozens and pick the good ones using a 3458A. For a DIYer this is not a problem. In other words, relatively precision (TCR) resistors can still be sourced.

Actually, the more difficult challenge in the NU180 project than resistors is INL! The real overwhelming advantage of the 3458A is its INL of ≤0.1ppm (measured 0.02ppm). So if the NU180's INL is far off, it simply cannot be called a success. Kleinstein previously defined a required INL for the NU180 of ≤0.2ppm – that looks like a reasonable but not easy target. Across all my NU180 versions, the INL characteristic almost always shows one feature: excellent INL (almost <0.2ppm) from 0 to +10V, but from 0 to -10V the INL behavior shows large, irregular variations. Some versions still exhibit the same good INL in the negative range as in the positive range (V0.70, V0.71), but more versions introduce gain error that pushes INL to 0.x or even 1‑2ppm levels. The origin of this gain error in the negative voltage range is something I've been trying to understand without success – this irregularity is a huge challenge. I've tried to control the trace lengths of the four main slopes to be equal in PCB layout, but the results show no correlation.

In the 3458A's integrating ADC, during the run‑up phase the number of switching events for the +12ref (two paths) and -12ref (two paths) integration current paths should be strictly the same for any voltage; the only difference is in the duration after switching. For negative voltages, the +12ref duration is longer and the -12ref duration correspondingly shorter – could this cause gain error? During the run‑down phase, only the S256 stage uses an asymmetric reference current injection process; the rest of the stages are unrelated to the main slopes. Could this introduce potential gain error? I currently have no clues on how to verify these questions, but obviously these points are very important. Until the cause of the gain error is solved, we cannot confidently say after laying out a PCB that this version of the NU180 will have good INL performance. In contrast, we can make reasonably reliable predictions about TCR based on the resistor parameters we have.

As for the noise performance of the NU180, I honestly haven't paid much attention to it yet. But one thing is clear: the noise levels across my versions are not very different – probably because hardware factors like the FF, ADG734, and CPLD are relatively fixed.

The above discussion is for the 'drop‑in replacement' NU180. I know there are about 3 versions of the NU180 design here – although the designs are slightly different, I think the issues encountered should be common. If we break the drop‑in replacement constraint, a resistor array like the OSOP becomes a good candidate. Even two LT5400s (100k×4 each) arranged symmetrically to handle one +12ref and one -12ref path could be an option. Because that involves replacing and modifying a number of components, I've only tested the OSOP‑based NU180 on my clone‑board A3. The results so far verify feasibility. However, performance aspects also involve some debugging on the A3 board, much of which is not directly relevant to this thread. If possible, I'd like to discuss that further in a new thread or some other relevant threads.

[Kleinstein]

For most of us some custom resistors or maybe selected standard ones (e.g. 5 ppm/K grades selected/checked for value and ZC matching) are likely the best option. Using multiple 20 K resistors could indeed suffer from too much parasitic capacitance.

Quite some variants here used a little capacitance at the slope amplifier to tweak the timing - such a minimal change to A3 may be acceptable.

Getting worse INL consistantly for the negative side is odd. Both signs are largely handled symmetric.
For understand that INL error it would help to know the "shape". So is it more like a different gain, some local peaks (like the DA effect) or more DNL issues ? I know it is difficult and slow to measure the INL (especially get it accurate).

I see a few ways how the NU180 could effect the linearity:
1) nonlinearity in the 50 K input resistance, like a thermal effect. A low TC (like < 5 ppm/K) is likely needed for this. This would mainly give a U³ contribution.
2) nonlinear R_on of the input switches, with the low R_on ADG734 or similar this should not be relevant. Ideally the supply modulation would correct for this. The low R_on switches may well get away without.
3) The additional capacitance of the switches can be an issue. This can make settling of the comparator more important and slower. As a last resort one may reduce the capacitance to ground on A3.
4) resistor mismatch: this would give DNL type errors that repeat with the run-up steps. It would be an issue mainly with 1 PLC and shorter.
   here resistor values matter (top of ladder part, 20 K in fast part to 80 K ratio).
5) power supply current effecting the clock (the 5 V supply has filtering common with the clock ). With my ADC (similar, but still simpler) I saw an abs(U) part from such interaction.
6) interaction between the supply and switch timing.
7) charge injection causing more disturbance to the integrator and thus settling more important
    charge injection includes capacitive coupling from the control signals to the switches and resistors. So that can vary with layout.

The settling related effects could depend on the input voltage, as the load to the integrator can change the OP-amps GBW and thus the settling.
In my ADC I have seen such an effect on the scope, but not all changes to the settling also cause an INL effect.

[MiDi]

I think MiDi has tried some large arrays like that, but found that the capacitance grew high enough to be a problem. There was also an attempt using an LT5400, but this apparently made the TCR worse, possibly due to miss-matches with other resistors (TCR matching within one array is excellent, but they have very poor absolute TCR).

In my array version the main problem were the ladder resistors, which were part of the arrays for all slopes.
Making the ladder resistors stand alone while keeping the others in a statistical array could work, maybe the fast slopes could be standalone too - this needs to be checked.

The critical resistors are the 50k input and the 4x80k slow slopes, they should track as good as possible.
In the original U180 those resistors are interwinded, which gives a very good tracking and helps a lot with changing temperature in the input resistors with changing input voltage.
If the INL errors are not "S-shaped", than I would presume that it is not input TC related.

The INL of one of Wanghars versions looked quite good, but the higher noise is concerning.
The drivers/switches could have significantly higher jitter than original U180s...

[wanghar]

The critical resistors are the 50k input and the 4x80k slow slopes, they should track as good as possible.
In the original U180 those resistors are interwinded, which gives a very good tracking and helps a lot with changing temperature in the input resistors with changing input voltage.
If the INL errors are not "S-shaped", than I would presume that it is not input TC related.

Absolutely agree with that. So the ideal solution is still to use a resistor array – that's the only way to make the 50K and the four slow‑slope resistors track as well as possible.

The INL of one of Wanghars versions looked quite good, but the higher noise is concerning.

The PCB version that showed good INL performance was V0.71. I sent the exact same Gerbers to JLC and had another batch made. I tested two boards from that batch – one still has very good INL（<0.2ppm）, but the other sits around 0.5ppm. So the influencing factors here are really subtle.

[Zondar]

I don't understand the faith in arrays such as the OSOP's. These have mediocre internal tracking of 5ppm. That's "only" 25 times worse than the foil resistor's 0.2 ppm. The absolute TCR is 25 ppm, which is worse than cheap 80k's at 10 ppm. Put 4x 10ppm 80k's in series/parallel, and you should (statistically) get 5ppm too.

At least the LT5400 claims 0.2 ppm tracking (between resistors within one package), but its absolute TCR is still 8 ppm, and with only 4 resistors per package, it's unlikely that you will find an arrangement that insures simultaneous tracking between all 4x 80's and the 50k.

Maybe the situation isn't as bad as the above sounds? A comparison with Wanghar's metal foil results would be especially valuable.

If cost is a concern, well, I think a total board cost of say $250-300, which is enough to splurge on foils for the 80's, or even the 80's, 20's and a 50k ($190 total), is reasonable, and even should be expected considering what it's going into.

About skew: If two or more switches are connected together (and some are), then there is at least the possibility of overlap due to skew. Fortunately, for the ADG's, the T_OFF time is faster than the T_ON time. If considered alone, this means that a break-before-make action lasting about T_ON-T_OFF should occur between switches as well. I might still drag my old ADG test board out and see if I can prove this.

A small question: It's not our goal of course, but the current boards at least elevate a dead 3458A to a "7.5 digit" meter in all respects, correct? Or better, an "8 digit" meter, if it's within 2x of hoped-for performance.

By the way, that replacement A3 board is gorgeous. It must have been a lot of work. Huge respect to those who designed and built it!

[iMo]

Frankly, I’m still somewhat skeptical that replacing such critical components as the U180 (or any similar components in any 6.5++ digit meter) can be fully corrected using only the service guide procedure. It’s quite possible that board-specific calibration coefficients are generated during final testing, based on additional measurements. In other words, your boards may be generally functional, but likely require adjustments to certain coefficients that the standard service procedure (which is dedicated to simple linear drift adjustment) doesn’t account for..

[Kleinstein]

The specs for the resistor arrays like NOMCT, ORN and OSOP are for the whole range of resistor values. This includes rather low values like 100 ohms and 500 ohms that are problematic due to the contribution of the bond wires. In several test arrays from these series, but with high resistance like 10 K to 50 K are performing much better (like TCR matching better than 1 ppm/K). I use ORN resistor arrays in my ADC and the gain depends on both a 5 K set and a 50 K set and I have not seen an overall TC of worse than 1 ppm/K, usually more like 0.1 to 0.5 ppm/K and there could be other contributions included.
With the 20 K values one needs to use combinations of 4 resistors and the statistical averaging tends to improve matching.

The TC specs for the S102 series foil resistors are know to be rather optimistic - actual TC for a smaller temperture range may be worse than typical box specs. TC matching could still work out OK and better than the arrays.

The LT5400 makes mainly sense for use in the inverter (10K/10K). Here it is only about tracking and the absolute value does not matter much (a tiny bit for the current compensation). The resistors for the 7 V to 12 V step are also separate and here the ratio accuracy is not even critical.

As far as we know (and there is quite some knowledge about the 3458) there are not numerical corrections done. The A3 baords are interchangible and even calcibration constants would not change. One would still need a calibration check to make sure things work, but when one working A3 is exchanged with another A3 board the old CAL constants will most likely still be valid. So no new adjustment needed.

It is still tricky to replace U180, as one would still need to verfy the INL and that is tricky at the sub ppm level.
It is unfortunate the some boards showed relatively high INL and the need to check the INL is thus very real, especially if it is not clear where the poor INL comes from.

[Zondar]

I generally work off of specs, which can normally be trusted, rather than anecdotal observations. On the other hand, I recall xdevs hosted a bit of an expose about over-optimistic spec-sheet claims.

Anyway, I am not against arrays per se. I am just reluctant to believe that parts with specs of 5 ppm, etc., will be superior to those with 0.2 ppm, even in the unlikely case that the former is very pessimistic and the latter is very optimistic.

So, what can be confidently said about the performance of arrays in 80k boards, or which would inform the 80k development? Which arrays, used where, are paying off so far, and by how much has been measured?

(I think the 100k approach is more suitable for the A3 board replacement case than a more typical repair case. But if the only external difference is that, say, two leads need to clip onto +/-18V, that seems OK to me too. Unfortunately, I think a little more than that would be needed, and I'd probably still think foils could be better anyway.)

[negativ3]

This may have been covered already but 30ish pages is a lot of detailed R&D to read through.
Has any accelerated aging/ovenising been applied, like a burn-in step to new prototypes?
At work, we have implemented such to analyse long term reliability and stability for circuits which has highlighted certain component issues to our benefit. We do tend to build & test in batches so outliers are easier to spot rather than single samples which can lead to false assumptions.

[Zondar]

Negativ3: I don't think that has been done, at least properly as your own outfit might.

I did run a board for well over a month, non-stop, to get a little insight into drift, but that's it for me so far. Also, I don't think any of us have made more than one or two boards of any single design, and not too many people would have multiple machines either.

[negativ3]

Negativ3: I don't think that has been done, at least properly as your own outfit might.

I did run a board for well over a month, non-stop, to get a little insight into drift, but that's it for me so far. Also, I don't think any of us have made more than one or two boards of any single design, and not too many people would have multiple machines either.

Understood, and the cost of running multiple samples can be prohibitive as well i'd imagine.

We run out boards in an ovenised setup, V/I/W monitored and critical signals are simulated (sweeps etc) so they are not installed as such, but very close to reality.

We have a more aggressive profile (delta Temp) for new designs and a gentle profile for production if that makes sense.

[Zondar]

I've made some progress towards a new iteration. Most changes are in search of lower noise. They included changing to MiDi's switch scheme, moving the latch and series resistors nearer to the switches, tuning their 8 trace lengths, and ensuring clean return paths. That did make the board larger, but I don't think it's a problem except for access to one or two A3 test pins.

The main 8 switches (still) uses Vdd2 and GND2, permanently. The latch can still run on 3.3V or 5V. Some other changes from my previous (0.4) version are: moving all capacitors from the back to the front, including pull-downs on the 5 left-over switch signals, removing a stray resistor, adding some extra capacitors and many other minor cleanups and improvements.

I'm not quite finished, and in particular I'm pausing to reconsider my stack-up, as I think that can be improved a little too. (I'm still not including anything for gate modulation.)

I will fabricate a version for the bulk foil resistors, probably still with overlapping footprints for other sizes. The 2512 footprints are large enough to allow 4x 805's to fit neatly in place of the 50 and 80's, which is what's shown in the screen cap below. I'll publish a version after I'm finished.

Any suggestions?

Thank you.

[MiDi]

For the Vref resistor networks are recommended, LT5400 as in wanghars design.
The ladder for the minor slopes should be optimized for fast settling as the rundown is quite short (HF design, minimize stray capacitance/inductance).

[Zondar]

Thank you MiDi.

The ladder resistors can be seen low and immediately to the right of the U180 socket pins. Their positions and traces are about as short and low capacitance as can be managed. It won't make much difference, but I can tweak it slightly more. I have foils on hand for the Vref resistors too, but I'll think about the arrays for a general design. 

I've been refreshing myself on low-noise stackup and layout. Advice these days is to not flood signal planes, I think mainly to avoid coupling through floating copper islands. KiCad's DRC finds all of these, though, so I'm not too worried.

Another contemporary thought is to skip the usual multiple-capacitor decoupling strategy, e.g. combining 0.1, 1 and 10 uF capacitors in the hopes of better decoupling over a wider frequency range. Instead, advice these days is to just use a single 10 uF capacitor per pin, or whatever the largest capacitance you can fit in the smallest, lowest-inductance package is. I'm not sure, but I see the sense in it. Here, if desired, the usual 0.1 uF capacitors can be substituted with another value, so long as they are still in a 603 package.

As for stackup, the debate in my mind is which sections and signals should use which reference. Most should use GND, but one of the AGND's or GND2 might be better for some. To help, I had thin PC boards (0.8 mm) made last time, in which the cores are only slightly thicker than the prepreg planes, and will do so again. The thin boards came out very well (no potato chips).

Simon recommended adding ferrites for power filtering, as wanghar did, but I consider this risky due to the possibility or even likelyhood of resonances.

I'm intrigued by X2Y capacitors for possible use with the switches in particular, to decouple VDD2 and GND2 to GND. I don't think it would make much of a difference though, as I do have decoupling for these via individual caps already, and those are on opposite sides of the packages too, so I'm passing on that for now.

I did also change series resistors to 805's, since swapping 603's, as I've repeatedly done, is annoying. That would come with a slight capacitance penalty, so I might change them back.

Has anyone used JLC's assembly with pre-ordered parts? They don't have the CPLD in stock, for example, but it seems these and most other missing parts can be pre-ordered, with a 10 day delay. It would be nice to have the boards come back mostly assembled.

[miro123]

I hope I am not disturbing this very informative thread.
I would just like to mention what the manufacturer Vishay says about different resistor film types.
In fact, the entire document provides interesting information. I hope it helps the discussion here.

https://www.vishay.com/docs/49562/49562.pdf

[Zondar]

I'm sure some here have seen this, but this paper is interesting too:

Measurement of Excess Noise in Thin Film and Metal Foil Resistor Networks, by Nikolai Beev.

[wanghar]

Has anyone used JLC's assembly with pre-ordered parts? They don't have the CPLD in stock, for example, but it seems these and most other missing parts can be pre-ordered, with a 10 day delay. It would be nice to have the boards come back mostly assembled.

No problem with pre-ordering parts from JLC. I guess JLC places orders with Mouser or Digikey for a decent number of components every day. Based on my previous experience with pre-ordering, getting into the pre-order process for unit price, lead time, and prepayment requires quite a bit of back‑and‑forth – it takes a fair amount of time. But I'm not sure if JLC has a more streamlined communication interface for overseas customers. For an IC like the ATF1502 with 0.8mm (31.5mil) pitch, soldering isn't too difficult – hand soldering after receiving the boards is still doable. That way the turnaround time would be shorter.

[Zondar]

Thanks wanghar.

Sure, if the switches are available and mostly only the CPLD is needed, then no problem, I can do that easily.

It looks like they do have ADG734's in stock, but I'm a little confused. The two options are described as "reel" and "reel7." As unit prices are provided, I presume that still means they are available individually. The two have different unit prices, though, for apparently the same part. Do you know what the difference is?

About stackup:

The available 6 layer stackup is: copper, prepreg, copper, core, copper, prepreg, copper, core, copper, prepreg, copper. Note that the cores are quite thick compared to the prepreg layers in the standard 1.6mm thickness PCB's. If you use the 0.8mm option (which I did for my V0.4 boards), the cores are only 20% or so thicker than the prepreg layers.

My current configuration (V.0.5, I guess, as well as V.0.4) looks like this:

1) Signal, flooded with GND - mostly digital but with some analog such as RUSN3 and SUM3
2) GND plane (uninterrupted).
3) VDD (5V) as a near-continuous plane plus VDD2 (4.4V) as a wide supply trace.
4) GND2 (-0.6V) plane plus SUM1-2, AGND1-2, AGND3 as wide(er) traces.
5) GND plane (uninterrupted).
6) Signal, flooded with GND - a little digital plus some analog like ZERO and RUSN1 and 2.

Among possible changes, I think the two signal planes (mostly digital, but with a little analog) would be better off if they were both next to a single GND plane. That's not a good idea with the 1.6mm thickness, but is more practical with the 0.8 mm thickness option. What I'm thinking about:

1) Signal, flooded with GND - mostly digital but with some analog such as RUSN and SUM3.
2) GND plane (uninterrupted).
3) Signal, flooded with GND - a little digital plus some analog like ZERO and RUSN1 and 2..
4) GND plane (uninterrupted).
5) VDD (5V) as a near-continuous plane and VDD2 (4.4V) as a wide supply trace.
6) GND2 (-0.6V) plane plus SUM1-2, AGND1-2, AGND3 as wide(er) traces.

This change should be easy. Moving other analog lines such as the RUSN's and SUMs, etc., would be more difficult but not impossible. But most of them use GND as the reference plane, and it doesn't look like any need GND2 or something else as a reference. I don't think the second option would be much different, but maybe it's a little better? On the other hand, if using (normal) thick-core stackups, the first option is probably better.

Any thoughts?

Thank you.