"NU180" - A U180 drop-in replacement for the 3458A.

[Zondar]

The odd CPLD output drivers when in the high state without a pull up or pull down could also produce a long time constant when drifting from some 4 or 4.5 V up to near 5 V.

That is a possibility. At present, I think all boards have them on the slope controls or else FF's, but not necessarily on the last 5 control signals. I don't recall if anyone has R's on those too (V0.5 does), but I've seen some with FF's on all control lines, which is even better. I think those still show the problem.

I still believe we are seeing a power-law process that is lost in the noise until it grows large enough to be seen (at the knee and beyond). What mechanisms might result in a ~0.02 ppm per decade drift?

One possibility is temperature related drift. In the case of continuous acquisition, things are likely to be warmer than if the idle time is extended more and more. Maybe wanghar's bulk-foil version could help discriminate this?

[DB4UCH]

For the log fit, you included all data, including the clear plateau from 0 to somewhere around 2 ms. Excluding that, e.g. starting around 3 ms, the fit would be very good, and especially would fit far better than the exponential over the last decade, where the exponential fit begins to fail badly. Also, perhaps aside from Kleinstein's floating node hypothesis, there is no possibility of any time constants on the NU180 boards to reach anywhere near 0.127 seconds.

Taking only the longer delays into account, it seems to be a log fit. I will now try the same with 10V applied. (although the LM399 noise might cause some problems here) Edit: Added the plots for the reference measurement as well.

Greetings,
Simon

[Kleinstein]

Instead of an external 10 V one could try a test probing the internal 7 V reference. This would eliminate most of the reference noise from the test.

[Zondar]

I measured my board's temperature coefficient via brute force.

I shielded everything except for the board, and then I saturated it with a heat gun. I measured the temperature via a probe attached to the PCB somewhere near the switches.

The conditions were 10 V in, 10 V scale, 10 NPLC, AZ on, no ACAL, using my legacy board containing surface-mount bulk-foil resistors.

The attached chart shows the digitized voltage over a temperature change of 45.1 C (reaching 95 C max). "Within spec" in this case would be <0.51 ppm / C without ACAL or <0.16 ppm / C with ACAL.

The board's drift was 2.2 uV, or 0.22 ppm per degree C, without ACAL.

I'd say that's pretty good!

(Edited: My guess is that the initial brief deeper dip is due to a transient change in resistor ratios, and then the broader plateau is after further stabilization. The value above uses the peak change anyway for the most conservative result.)

[Zondar]

I'm reworking my V0.5 layout yet again, and have a few questions for the collective.

20 MHz clock input: This is coming from a 20 MHz oscillator after passing through a 160 nH inductor. The oscillator (Fox F5C-2E, at least in my case) has CMOS outputs with rise and fall times that are fairly slow at 10 ns each.

A rule of thumb is that the round-trip time over a trace and back should be <1/10 the rise/fall time of the signal for reflections to be ignored. Round trip on my current board is ~100 mm, which for FR4 (~150 mm/ns) corresponds to about 0.67 ns round-trip time (vs. 10 ns). This suggests that an impedance-matching series resistor is not necessary. However, this clock, viewed on a scope, is rather sloppy.

Initially (V0.4), I placed the inverter at the input pin, presuming to clean up the sloppy signal nearest its source, and I included a reflection-control resistor at the inverter's output. In V0.5 I moved it to the end of the wire right by the FF (with no resistor at the CLK input pin or after the inverter).

There is also the problem of the clock needing to go to the CPLD too. With the inverter near the input pin, the CPLD's clock can branch off before the inverter, leaving the clock to the FF cleaner. Otherwise, unless another inverter is added somewhere, the clock line must be shared.

It's all a trade-off, but jitter here should be controlled, so what approach do people think is best?

Series resistors from CPLD to FF: At present, I have these in place. However, they are not really needed, since there is plenty of time for these signals to settle before they are latched by the FF's. Any issue with removing them?

Series resistors from FF to switches: From the standpoint of reflections, these are not needed, since there is only a few mm distance between the two. Controlling the rise and fall times (natively about 1.5-2 ns) could still have some benefit. Opinions?

Additional FF: I don't think people have found any benefit from adding a second FF, have they? If not, it can remain left out.

Cleaning up floating pins: Pins 5, 7 and 12 (the mid-points of the 50k resistor), pin 1 (substrate bias),  pin 39 and 41 (xua, xub), and pin 32 (mod_sense2) were mostly left floating per the "clip" document, but they can and probably should be grounded. At the moment, I also have mod_sense1 grounded, but this can and probably should be left floating, as it's an output from an op-amp and there is no reason to pull it down. Any disagreement with any of this?

Modulation: I still haven't heard that there is a definite benefit from the attempts to perform this. Have there been? I remain unconvinced and would still leave it out unless there is.

Temperature Coefficient: Do people agree, or disagree, that the technique I used to test TC in the last post was reasonably valid? How does the result (about 0.22 ppm/C) compare to genuine U180 results?

Wanghar measured 1.8 ppm/C using standard 0.1% 80k's. He achieved better than that using bulk-foil ones, but I've only seen a relative figure of within 0.4 ppm of a genuine U180-equipped machine.

Since the 80k's in particular remain problematic using off-the-shelf components, I think my next board will commit more fully to foils, with both through-hole and surface-mount options possible on the same board. Is there any other realistic choice? Which resistors do people feel require this treatment? I'm thinking the 50 and 80k's should be the minimum (50k foils are available off-the-shelf, at least). Note, though, that I used foils for all of the important resistors in my legacy board as measured above.

[aronake]

Temperature Coefficient: Do people agree, or disagree, that the technique I used to test TC in the last post was reasonably valid? How does the result (about 0.22 ppm/C) compare to genuine U180 results?

I did some TC testing on my 3458As.

Put voltage reference in TEC box and kept constant 23C. Then used AC to make my whole lab into giant "TEC box".

One "sweep" with recurring ACALs, one without. What I then saw as TC PPM/C vs internal temp was:

                                                                                                     My interpretation
TC no ACAL 10V measurement:    0.10   0.13   0.04    0.05   0.06       The whole system
TC CAL72 (with ACAL)                -0.01  -0.06  -0.02   -0.03  -0.03       TC of A3
TC ACAL 10V measurement          0.09    0.09     0.06   0.03   0.03     TC on Voltage ref

A year later I repeated the same and got similar results.

So with some correlation TC no ACAL 10V + TC on CAL72 = TC ACAL 10V measurement.

Or maybe better written System TC (TC with no ACAL) = A3 TC (opposite direction of CAL72 TC) + A1 TC (I have not been able to measure this) + VREF TC (Assume ACAL on 10V measurement give this)

So i think doing an ACAL DCV before and after temperature change and calculate PPM/C is a good way of measuring TC on an A3 board.

I think I am quite lucky with the TC on the 3458a I have. I have seen many cases with TC being quite a bit higher.

According to specifications TC should be max 0.5 without ACAL and 0.15 with ACAL. So if my thinking is right, The reference board would then be allowed to have 0.15 TC and the A3 and A1 would share 0.35 TC. It seems to me that A3 have quite a bit more TC than A1, so maybe an A3 with 0.25 PPM per C or so would be considered to be within specification.

Some random, not completely verified thoughts on this.

Thanks for awesome work by you and the other here to bring this forward!

[Kleinstein]

The CPLD to FF lines should get away without series resistors. However the CPLD output should ideally all have pul down resistors, so that they do settle fast. An output withput pull down would settle slow and the capacitive coupling is than a problem as it depends on the time since last switching.

The FF to the switches can likely also get way without series resistors - the distance should be small, but the rise time is shorter. So if there is space, maybe have resistors.

I don't see a need for addional FFs also for the less critical signals. The extra FF would only need more power and load the clock.

The modulation should not be needed for the low R switches. Of cause the modulation sense pin (pin 30) should still be connected to GND.
One could consider a resistor to ground to this way enable the modulation.
With the pin floating, the voltage at pins 28/29 would get really far off from 5 V. So these pins would no longer be suitable as supply.

[Zondar]

Thank you aronake for that data. That looks rather good.

I suppose I was misquoting the ppm's since that's always relative to the reading in the end. So wanghar's 1.8 ppm with standard 80k's is significantly out of spec, but my 0.22 ppm (2.2 uV without ACAL) is within.

Of course you are right that all sources of TC must be included. On that point, the first half of deviation I showed above was while the board was still heating up. The deviation actually dropped as it reached the final temperature, leading me to believe that I was partly seeing the result of resistor ratios changing. e.g. because some resistors had less mass and heated more quickly than others. Still, by your math the 0.22 ppm I measured appears low enough for the entire machine to remain in spec.

[Zondar]

Thanks Kleinstein. One question:

Of [course] the modulation sense pin (pin 30) should still be connected to GND.

That only applies if modulation is actually used, and without that, the pin can remain floating, right? I don't see why it should not be. On the other hand, U170B (a related op-amp) connects to that pin through a 51k resistor, so I don't see a problem with it being grounded either.

[aronake]

Thank you aronake for that data. That looks rather good.

I suppose I was misquoting the ppm's since that's always relative to the reading in the end. So wanghar's 1.8 ppm with standard 80k's is significantly out of spec, but my 0.22 ppm (2.2 uV without ACAL) is within.

Of course you are right that all sources of TC must be included. On that point, the first half of deviation I showed above was while the board was still heating up. The deviation actually dropped as it reached the final temperature, leading me to believe that I was partly seeing the result of resistor ratios changing. e.g. because some resistors had less mass and heated more quickly than others. Still, by your math the 0.22 ppm I measured appears low enough for the entire machine to remain in spec.

My thinking is that measuring PPM/C on CAL72 is a good way to measure TC on the A3 board as no external source is needed, and drift in voltage reference is excluded. Part of CAL72 TC may come from A1 though, but seems to be the smaller part in most cases.

[Zondar]

While the whole machine must be measured in the end, I do think that getting data for "only" the NU180 board is quite useful, and the result was encouraging. If I can get my old board with standard resistors running again, I'll try to compare the two.

Drift is often the main reason driving a U180 replacement, so TC is important. I'm very interested in any further TC data people have gotten with their alternate configurations, such as by using parallel / series resistors. Avoiding custom resistors while getting adequate performance is a worthy goal. But I mostly think that a "pro"-grade NU180 will still need 80k foils for best results. All other important resistors are available off-the-shelf with adequate specs.

By the way, it's interesting to consider the difference between parallel and series resistors.  Parallel ones offer lower self-heating effects(if that's a factor; the general environment is likely to dominate), but series ones offer reduced capacitance. The bandwidth is different too.

For those using 20k's to make up the 50k resistor, I might suggest putting the pair of parallel resistors between the two series 20k's, not at the beginning or end, for (I think) a lower over-all capacitance.

[Kleinstein]

For the self heating the question for parallel or series connection makes no difference: the power is split evenly between the 2. There is a small difference with the parasitic capacitance and maybe excess noise (high value resistors tend to be worse and thus a slight advantage for the series version). On the other side thermal EMF effects would perfer the parallel version, if they are not directly side by side or on top of each other. Both effects are likely small here.
For the parasitic capacitance it make a difference where it is: capacitance at the switch side come with a little more noise and more capacitive coupling. Capacitance at the reference voltage / ADC input is less relevant, unless rather large. So one would prefer the 20+20 +10 K for 50 K version with the 10 K to the ADC input and not in the middle.

[Zondar]

For the self heating the question for parallel or series connection makes no difference: the power is split evenly between the 2.

Ah, yes, that is correct. Two in parallel can handle twice the power, but at a given power the self-heating per resistor is the same.

Any idea how much self-heating could be a TC factor? I guess the 80k's only see ~150 uA? So I'd guess it's not likely to be a factor relative to everything else going on in the chassis and general environment.

[Kleinstein]

Self heat is essentially not a factor for the 80 K and other reference resistors. They see an essentially constant power and thus have the slightly elevated temperature all the time. 150 µA and 12 V are 1.8 mW and thus a relatively small temperature rise (maybe 1 K range or a little less).

Self heating is mainly a factor for the 50 K resistor at the input. This resistor sees a variable voltage and the change in temperature with the TC can contribute to the INL, especially an U³ part. With resistor array one could have coupling to the reference resistors, so that mainly the TC matching would matter and not the absolute TC. With separate resistors this would likely only be weak coupling and not much compensation. The TC matching would still be relevant for the gain TC.

So one wants a good TC for the 50 K and also a large size / series mix instead of a single resistor can help to reduce the temperature rise.
The power coefficient can have additional contributions than just the simple delta T time TC, as the temperature rise is not uniform. The simple picture is still usually OK for a rough estimate.

[Zondar]

I looked up data for the 2512 VSMP foils that I used for the 50 and 80k's.

The claim is that at full power (750 mW for 2512's), the delta due to self-heating is 5 ppm. So, to keep the delta to say 0.1 ppm, a load of up to 15 mW is presumed OK.

For the 80k's, the spec implies that self-heating would cause a delta of 0.012 ppm, which would be negligible.

For the 50k, supposedly up to 15 mW can be tolerated for a 0.1 ppm delta, as mentioned. That's no-doubt under ideal conditions, and to allow for that, maybe half that - 7.5 mW or so - should be OK.

The Z201 leaded bulk-foil resistors share the same specs concerning TCR and self-heating.

(I continue to suggest these sorts of parts because there is essentially no practical way to arrange all 80k's and the 50k to all track together using off-the-shelf arrays.)

[Zondar]

I've been working on V.0.6:

* Improved clock distribution. The clock inverter is back at the clock input pin with a reflection-control resistor. The wire from resistor to the FF is clean, using only top metal, directly over a solid ground plane and with grounds on both sides throughout.

* I redid some of the CPLD's wiring, and a few other things, to avoid using a rat's nest of bottom metal jumpers. This will require minor changes to the CPLD code, namely relabeling which pin corresponds to which signal.

* Separate optional regulators for the inverter and the flip-flops. This was semi-necessary since the inverter is near the clock pin and the flip-flops are near the bottom. It does allow more flexibility, e.g. the inverter can remain at 5V while the FF can be at 3.3V.

* Multiple footprints allows the 80k's and the 50k to be either 2512 or 1206 or through-hole resistors (3.5 mm pitch for Z201's). Unused footprints can be left there or else deleted. There's enough space to put parallel or series resistors in their place.

* No series resistors from CPLD to FF's. Series resistors and optional pull-downs on non-FF controls.

* No floating pins and many more minor tweaks.

To do: Streamline KiCad footprint library issues, etc. More fine-tuning here and there. More community input, and/or things I've forgotten.

(The attached screen capture hides the 50/80k resistors so the metal and through-holes can be seen.)

[qzh3887896]

I've built several NU180 modules. One of my 3458A multimeters is fully repaired, and all self-calibration routines passed without issue.
And second 3458A ,the other unit has an odd fault. Initially, it failed its power-on self-test entirely. After swapping in a different NU180 board, the self-test completes successfully, yet the ohms self-calibration throws Error 205 at the ZERO DCI 1 µA step, with the message CAL VALUE OUT OF RANGE 63.
I probed the A3-DC_AD port with an oscilloscope and cross-referenced readings against the fully functional unit. During the ZERO DCI 1 µA calibration phase, the good meter measures -300 mV at this node, while the faulty unit reads +400 mV. I believe the internal electronic guard rail threshold is roughly ±350 mV; the 400 mV reading exceeds this limit.
I have also observed another strange behavior. When this 3458A is first powered on, the open-circuit resistance reading shows 500 MΩ. The measured resistance gradually rises as the unit warms up. If I use a hot air gun to heat the op-amps surrounding the NU180 module on the A3 board, the upward drift of the open-circuit resistance accelerates significantly. At this point, the voltage measured at the A3-DC_AD node is 5.2 V. As time elapses, the open-circuit resistance eventually exceeds 1.2 GΩ, triggering an over-range indication of +O.VLD.
I cross-referenced readings with a fully functional calibrated unit: its A3-DC_AD port measures 5.8 V. This voltage discrepancy likely explains why the faulty unit starts at 0.5 GΩ cold. The root cause primarily lies on the A1 board, with minor secondary contributions from the A3 board.

[coromonadalix]

I've built several NU180 modules.....

witch versions did you build  ?

[Zondar]

Another iteration, mostly aimed at cleaning up control lines and lowering sources of digital noise:

* Added series resistors to all CPLD outputs (now including to the FF's), and moved all of them close to the CPLD's output pins. Also moved the series switches closer to the FF outputs.

* Redid the trace-length matching from resistors to switches.

* More wiring simplification.

Next:

* I want to take another look at how the switches connect to Vdd2 and GND2. I don't like how one of the traces feeding them partly interrupts an interior plane, and I think I see a way around that.

* I'm considering adding FF's to the other 5 control signals, regardless of whether it helps or not. The FF is inexpensive and not really more bother than the pull-downs. I probably won't, though, as that would need an additional inverter (don't want to share clocks), and I don't think even the pull-downs are necessary for these lines. If pull-downs are used, I'd recommend higher resistance than the 5k that has been used; maybe 100k will do.

* I remain interested in whether the switches can be run on +/- 2.5V instead of +4.4 and -0.6. The idea is to make the on-resistance flatter about 0 V. This is complicated by the fact that a lead to a negative supply, e.g. -18V, would be needed.

* I intend to reconsider which inverter and FF I'm using, as I'd like to arrange the possibility of 2.5V signals from FF's to the switches. I'm also tempted to make them permanently on 3.3V or 2.5V rather than include the jumpers.

* When I switched to MiDi's version of the switch configuration, it messed up the prior relatively elegant resistor arrangement somewhat (some longer traces were required plus a jumper or two). I dread looking at this again, but I might anyway.

* I'm wondering about further noise reduction on power supplies. Wanghar took some steps towards that, but I'm leery about adding resistance or inductance in their paths since I'm not an expert on this topic. On the other hand, at this point the only component that requires 5V (vs. optional) is the CPLD. I would not be worried about more aggressive filtering on that only.

* If someone following this thread is an expert layout artist, or a master at power supply filtering, and who would like to review the layout, please contact me privately.

[Kleinstein]

I see little need for external flip flops also for the other control lines. These signals (inputs, ladder connect, 10 K compensation resistor and reset) are only switched twice (on and off) for a conversion. So jitter is not as relevant there. One may still want pull downs for these signals.
An extra FF is cheap, but it loads the clock and consumes power and produces EMI. I see no real advantage from the FFs, except faster settling. Simple pull downs should work as well with less negative effects.

Even for the FF signals the question could be if it is worth having pull down resistors, at least as an option. Not populating the pull-downs is easy. With a FF it is more difficult to choose not to use it.

I don't think a +-2.5 V supply for the switches would be good. With most such switched the charge injection is smallest in the 0 - 1 V range. So the -0.6 V could make sense.
The VDD2 and GND2 part would offer a -0.6 and +4.3 V supply to shift the switch supply to about where the charge injection is smallest. With only -0.6 V there should be no need for an extra level shifter. The FF may have to run with the same +4.3 V supply. The CPLD with a pull down, could be OK to interface with the 4.3 V supply. AFAIR the output level would be in the 4 V range and thus OK - still have to check.

Supply filtering could be an issue with VDD1, as VDD1 has not much filtering from the oscillator to U180.
The possible issue it the NU180 effecting the oscillator via VDD1 and this can cause INL errors.
I would consider a capacitor at VDD, a parallel connection of a resistor and ferrite and than another capacitor to ground.

[Zondar]

Kleinstein: Looking at charge injection again is a good idea.

For complementary CMOS switches ("transmission gates"), there is a direct design conflict between charge injection and on-resistance flatness. For the ADG's, the priority was clearly flatness. That meant that the charge injection will be larger on the P-channel side (as the source voltage increases towards Vdd). This tendency can be seen in chart 16 in the ADG documentation.

Eyeballing that chart, it looks like the charge injection in the -0.6, 4.4V case would be about the same (perhaps slightly better) as the +/- 2.5V case, but in the opposite direction.

This brings up an interesting question: I think the zero offsets people are seeing are always in one direction (negative), right? And that the NPLC issue is also always in one direction, also growing negative, right? Could this be because the charge injection is also always in one direction (also negative)?

If so, then because the source voltage is always 0V, we could in principle tune the +/- supplies on the switches to null out the charge injection.

(One point against that idea is that the genuine U180 will also have a constant charge injection bias, also negative. Another is that the AZ should cancel it anyway, but apparently doesn't. Still, it's an intriguing idea.)

[Kleinstein]

Charge injection could be an issue if too large. It is very hard in which direction the effect would change the result. The point is that if the pulse from charge injection is large, the voltage at the ntegrator input can become larger than some 25 mV and than the BJT based OP-amps (especially U110) do become nonlinear as the input stage saturates. What the final result would be is hard to tell, but it could be nonlinear.
The AZ mode would correct most of the simple effect. Espcially for the offset with a short one has to readings at essentially the same voltage.
I think the PLC dependent offset war kind of followed back to some of the CPLD outputs withput a pull down. This gives slow settling an an effect of the delay to send the result.

Flatness of R_on does not matter at all, as the switches are all used at essentially ground potential.

[Zondar]

It seems that pull-downs and/or the flip flops changed the NPLC effect a little, but neither eliminated it. Simon could provide data on that. If it's still a timing issue related to those signals, the latest version might possibly help.

We don't know which has higher charge injection, U180 or NU180, but my educated guess is that U180 would. That's because it uses a single quite large N-channel switch vs. a complementary pair, which as I mentioned partially cancels out charge injection.

It's a little risky, but it's probably possible to push and pull on Vdd2 and GND2 (lowering either only Vdd2, only GND2, or both) to see if that changes either effect. It's easier if those pins are disconnected and if the inverter is at 3.3V, but you still can't go too far below 4V because the CPLD's outputs will start to power the FF instead of Vdd2. Probably down as low as 3.7V should be OK (maybe slightly lower), again as long as the inverter is at 3.3V. If it's at 5, that would be a much bigger problem. The negative side doesn't have those constraints, except for not exceeding a total of 5V by too much.

I think this remains a suspect until something like that is tried.

Edit: I tried it. Changing Vdd2 in the range of 4.25V (the lowest I could go before something started complaining) to 5 Volts resulted in 6 pV difference, which is just statistical noise. Likewise, changing GND2 over a small range did not seem to do anything. So evidence does not support the charge injection idea. It does support that the digitization does not depend on the switches power supply, e.g. via small changes in on-resistance, over small supply variations.