"NU180" - A U180 drop-in replacement for the 3458A.

[ch_scr]

One could "sandwich" the digital traces in between Gnd planes, and strategically use "longer distances to gnd"-layers for lower parasitic capacitance traces

[nosnowfall]

Hi Zondar

It looks like they do have ADG734's in stock, but I'm a little confused. The two options are described as "reel" and "reel7." As unit prices are provided, I presume that still means they are available individually. The two have different unit prices, though, for apparently the same part. Do you know what the difference is?

"reel" and "reel7" are ADI's terms for different size bulk reels (one bigger one smaller) but it makes no difference when buying individual pieces. I believe the price difference comes about when distributors get ahold of partially used reels, because then selling cut tapes is easier than re-reeling several into a single tape for bulk sale.

[qzh3887896]

 :)I'm very glad to find so many posts about repairing the HP 3458A here, and I really appreciate all the experts sharing their experience and open-source work.
I'm using DB4UCH's NU180 V.0.4.1 design, and my 6-layer PCB has already been manufactured. Unfortunately, the precision resistors I purchased do not meet the required specifications. I could only get 0.05% tolerance parts so far, and I am now contacting manufacturers to inquire about custom higher-precision versions.
Additionally, the CPLD chips I bought, marked ATF1502AS, turned out to be laser remarked refurbished units. When trying to flash the JED file with ATMISP, the programmer only recognized them as ATF1502ASV. This confirms they are actually the 3.3V ASV variant, which is incompatible and cannot be used in this 5V circuit.
I have ordered genuine brand-new ATF1502AS from a different seller and am now waiting for delivery. Looking forward to getting this NU180 replica working successfully.

[Zondar]

I've been working on V0.5, and it's basically finished. Here's an updated look. For the 50k and 80k's, it is designed to use either precision 2512-size bulk-foil resistors or else 1206-size "normal" resistors. This is accomplished by using overlapping footprints for the two sizes. That shows up as "errors" in KiCad, but it's actually fine. (One final "error" is that the socket-pin array is not in the main library, but that is also not an issue.) All other critical resistors are currently in 1206 size.

About stackup: I decided to go with the original stackup, since that one is better if people build normal-thickness boards. The alternate one was potentially better, but mandated that core layers be as thin as prepreg layers.

A question: Most boards that do not include modulation, including mine, have ModSense grounded. However, since Mod_In is not used, leaving it floating seems more sensible. Thoughts?

Any other suggestions? 

NB: Simon (DB4UCH)  has agreed to modify this file much like he did to the V0.4 version, e.g. to include resistor arrays where beneficial, etc. If you aren't intending to go down the custom 80k route*, you may want to wait for his modified version. If you do want this version, please contact me directly (it's perhaps too soon to post it publicly).

(* Custom bulk-foil resistors in size 2512, as needed for the 80k's, are available at texascomponents.com for about U.S. $25 per part. The 50k's footprint is also 2512, just for "improved matching," but 2010 is possible for 50k, and costs about $5 less.)

Thanks.

[aronake]

Has anybody tried to place components both on top side and bottom side of the PCB? It ought to be possible to shorten PCB traces quite a bit doing this. In may designs it looks like the traces may be 5 times as long as wires inside U180.

[Zondar]

There's zero possibility that the wires could ever be as short as in the real U180.

That said, most of the wires that are visibly "long" are not in the critical path. For example, nothing related and prior to the flip-flop has strict timing or settling requirements, since the flip-flop latches and re-synchronizes those signals.

The tracks in the critical path, related to the resistors, the switches, etc., are as short as reasonably possible. Some slight further reductions could be possible if components are placed on the back, but that also comes with a few compromises. For example, I tried - mostly successfully - to wire everything from the flip-flops onward in the top copper only, avoiding transitions between layers, and directly over a single continuous ground plane, to provide the best signal integrity I could.

There are some tracks that are longer than necessary, such as those after the flip-flop, but those were to equalize track lengths. (It's far from certain that the equalization will help with noise, etc., but there's not much down-side, and it's worth a try.)

Where does the length pain me? The clock line in particular is relatively long, plus it has to go to two pins. I don't like that, but dealing with it was judged a better compromise than moving the flip-flop close to the clock pin.

Of course, if you have specific ideas about improvements, I'm eager to hear them.

[qzh3887896]

I hand-soldered the unprogrammed CPLD into a fresh (updated version) board, with no other components, and it draws the appropriate amount of current. I haven't programmed it yet, but I'm pretty sure it is functional.

I remain baffled. I've checked over and over, and there is no difference in the CPLD's connectivity between the two boards. The additional components attached to the CPLD consists of decoupling capacitors, 33 Ohm resistors on its outputs, programming pins, and the switch's hi-Z control inputs. None of that should cause any problems in principle.

I've wondered if my using a stencil and hot-plate (peaking at ~230 C for standard tin/lead solder paste) damaged the board or any parts, but that shouldn't be likely. The connections all seem good anyway, and the extracted CPLD seems fine too.

I don't have enough parts to populate the rest of the board unless I transfer some of them over from the built board. I guess I should do that. Perhaps I'll start by removing the switches one by one and see if anything changes.

I did order more "functionality grade" parts this morning, which should hopefully come in 2-3 days. I have one clean board left, which I'd want to save for fresh components, to be built using the stencil.

The custom precision resistors should arrive in about 2 weeks. I'd definitely want to be fully confident that a board will be good before using them. But that needs to wait until I test a "functionality-grade" board in my 3458A, and also make updated boards with 2512 footprints for the 50 and 80k's.

Edit: It occurred to me that I can remove the 33 Ohm series resistors from the CPLD's output path, and that would disconnect it from the switches. I might do that first. I'm still puzzled, though, and mostly don't think any of that will help.

How was the issue of this CPLD not being programmable later resolved?

I just bought five ATF1502AS chips. I soldered the first chip onto the PCB and prepared to program it. I supplied 5V power and found that the current was 0. When I tried to program the firmware using the programmer, it indicated a chip model mismatch and couldn't program. Then I swapped in the second chip. As soon as I supplied 5V power, the current reached the CC limit of 0.2A, and the 5V voltage dropped to 2.6V. I checked the soldering and everything seemed fine. I was completely puzzled. Later, I lifted all the unused ground-connected I/O pins of the CPLD and left them floating. The current returned to a normal 20mA, but it still wouldn't program. I suspect that the CPLDs I bought this time are defective — they look new on the outside, but have actually been programmed with other firmware internally, causing some pins to output current and pull down the voltage (because I had grounded all unused I/Os in the circuit). Tomorrow, I will continue testing the other CPLD chips I purchased.

[Zondar]

Hi qzh,

Earlier on, I had frustrating problems with the CPLD too. Assuming you have legitimate chips that haven't been pre-programmed, you also have to be careful how you program it, or you may not be able to reprogram them yourself again either.

If chips are pre-programmed and seemingly won't allow reprogramming, you may be able to reset them by applying 12V to pin 38. But please read the chip's documentation to find proper info on how to do that.

After being programmed, the chip should use 20 mA when idling, and about 23 mA when in operation.

I presume you are using DB4UCH's programming file? That should be correct, but make sure that you have the following line, exactly, in your code:

Device   f1502isptqfp44 ;

Read this thread for more info, but work from DB4's file:

https://www.eevblog.com/forum/metrology/nu180-a-u180-drop-in-project-for-the-3468a-dvm/msg6107001/#msg6107001

I hope you have better luck soon.

[qzh3887896]

According to the circuit structure, can I consider that U1 and U2 are the same, meaning that S5 and S7 are interchangeable, S4 and S6 are interchangeable, S9 and S11 are interchangeable, and S8 and S10 are interchangeable?

[Zondar]

No, those are not interchangeable.

Also, if you are looking at my last schematic: don't, since those signals are connected differently from the V0.4.1 that you are building, and so a different program is needed for the CPLD. Refer to the schematic that goes along with the version you are making.

[qzh3887896]

The new ATF1502AS has arrived. The good news is the program can be burned successfully, but the bad news is the board still cannot work properly. I have long suspected that my PLD file is not the version compatible with the V0.4.1 PCB. There may be I/O port mapping errors in the program. I have attached the content of my PLD file; please help me check and find out where the problem lies.
Thanks !!

[qzh3887896]

Today I wanted to use my old universal programmer to erase an ATF1502AS, and I ran into a strange issue: whenever I set VPP to 11.5V, it would report an overcurrent detection error. But if I set it to 5V, it worked fine without any overcurrent issue. That even made me wonder whether newly manufactured chips might differ from the older ones. So I asked DeepSeek, and here’s the reply: “Newly manufactured chips now have an integrated charge pump that generates the 12V required for erasing internally, so there’s no need to supply an external 12V for erasure.” What an interesting answer!!

[qzh3887896]

Is there a clear resolution to the clock edge question, or is that still being investigated? I've put aside my stubbornly non-functioning V0.4 board for now in favor of updating the design.

No, I don't think there is a clear resolution yet, as running the FFs and CPLD with inverted CLK is more stable than running them without it, but I don't know how much this stability improvement is down to the delay that is added by the inverter vs the inverting itself.
I will try to just install a buffer on my future v0.4.1 (with switched around references) and see how this behaves.
KiCad files and schematic attached below (for this v0.4.1), I will order the PCB for this new revision soon.

Greetings,
Simon

Edit: I updated the design slightly (added another C) (attached below) and ordered a new set of PCBs.

Hi，Simon ,
I’m using the V0.4.1 version of the PCB that you designed. It seems I didn’t download the correct PLD file. Could you send me the correct one? I’ve read through the entire post and might have gotten confused with other versions. So I’m really hoping for your help. Please, and thank you!
     
Thanks !
Jack Qin

[DB4UCH]

Hi，Simon ,
I’m using the V0.4.1 version of the PCB that you designed. It seems I didn’t download the correct PLD file. Could you send me the correct one? I’ve read through the entire post and might have gotten confused with other versions. So I’m really hoping for your help. Please, and thank you!
     
Thanks !
Jack Qin

The CPLD code you seem to be using is from a version without flip flops. Try using the code I attached to this post: https://www.eevblog.com/forum/metrology/nu180-a-u180-drop-in-project-for-the-3468a-dvm/msg6195619/#msg6195619
This code should work for the v0.4.1 revision. (The switch mapping is changed as I saw better linearity with this configuration.) I always compile my CPLD code with custom flags to not disable the JTAG, although changing the CPLD type also should work.
Btw. to what position have you set the clock jumper on the bottom side of the NU180? Here the preferred position is Inv. The other jumpers look fine.

Good luck!
Greetings,
Simon

[qzh3887896]

Currently I have the jumper set to NOR. Tomorrow I will change it to INV and re-flash the firmware according to your knowledge. Thank you very much!
JackQin

[qzh3887896]

Hi ，Simon ，
Thank you for your support！
Good news: After two days of debugging, my NU180V0.4.1 is now able to generate normal integration waveforms. The labels for R15 and R16 on the PCB need to be swapped, as they don’t quite match the schematic. Additionally, a few resistors didn’t have the exact required values, so I used two resistors in series to fine-tune the resistance. Bad news: Although the display can now show voltage values, the self-test fails with an overvoltage indication. Upon inspection, I found that when the main signal channel’s external input is shorted, the static voltage is 7.9mV. After being amplified by the following stages, the voltage at the DC_AD pin reaches the supply rail. This suggests an issue with the DC board. Next, I need to try to fix this problem.
Thanks！
JackQin

[DB4UCH]

I have now designed my sub revision of Zondars v0.5 NU180 called v0.5.1. I use resistor networks for the +-12V references (LT5400), and 0805 resistors for the slopes / +5V reference. (The 160ks now need to be stacked like the resistors for the lower slopes.) Other than this it's pretty much unmodified from Zondars base design.
I will order a set of PCBs in the next few days.

Greetings,
Simon

[Kleinstein]

Upon inspection, I found that when the main signal channel’s external input is shorted, the static voltage is 7.9mV. After being amplified by the following stages, the voltage at the DC_AD pin reaches the supply rail. This suggests an issue with the DC board. Next, I need to try to fix this problem.
JackQin

Getting a voltage at the input, behind the protection suggests that there is some high leakage current. That would be something like 1 of the switching JFETs (or a comparator for the controls) that is not working.

[qzh3887896]

You're right. After replacing one JFET and one dual JFET, the voltage is now normal.Thanks！

[Zondar]

A few things:

I've felt it is important to take note of where the project stands in terms of performance. Therefore, I've updated the first post to include some of the recent measurements. As I did not make these measurements, those who did (mostly wanghar and MiDi) should please review them to catch any errors or misunderstandings I may have made. People should please also suggest anything else that should be included or changed.

About V0.5.1: Note that the pull-down resistor positions are optional. No improvement has been noted by using them on these switches, but they are there to be tried if desired. If you do use them, I'd suggest using larger-valued pull-down resistors than before to reduce the current they consume when high.

I've also wondered a little about whether series resistors are really needed after the flip-flop. Normally, I would not include those, as the fastest possible edges are desired. Here, the damping of any ringing (the usual point of series resistors) might still be consideration, though I don't think we have measured a need for this or for the result of it. Thus, we've been including them due to what I call "superstitious behavior", i.e. doing something now simply because "that's how it was done" rather than for a specific identified current need. People haven't seen any notable difference between say 22 Ohms and 100 Ohms, but has anyone tried using no series resistors? Any opinions?

Also, while V0.5.1 uses a few matched arrays to good effect, it does not do much to deal with the 80k problem, which really must be addressed. It's clear that ordinary 80k's (or doubled 160's, etc.) will work well in most ways, but I don't think wanghar's results can quite be reached without something better like his through-hole foils. Perhaps a V0.5.2 version can include options for that. My V0.5 allowed for either 2512 or smaller resistors, i.e. for foils or normal ones. That could be changed to allow for the through-hole resistors that wanghar used, too. Are there any better (non-custom) options left?

[hanzhu]

大家好：
我根据你们发表的文件（主要参考wanghar的V0.71版）自己设计做了一个版本，还用 wanghar 的 V0.71 版本 Gerbers 文件做了一版。
我自己做的版本把模拟开关和CPLD都进行了重新布局，我是用SN74AHC273做了双触发器和SN74LVC1G14反相器，并在触发器输出端口加装了下拉电阻和串接电阻。自己按照MiDi发布的PLD文件进行了改写测试。
现在对发现的问题进行一下反馈：

1.你们测试的3458A万用表是哪个版本，我自己用V7版本开机202错误无法进行测量，我购买了M27C4002编程到V9版本进行测试，开机没有 202 错误，偶尔会出现 114 错误，经过对 PLD 程序修改已经可以正常测量不会出现 114 错误。
2.由于没有 wanghar 的 V0.71 版本 PLD 文件我自己按照 wanghar 图纸和 MiDi 文件进行了编写测试，同样发现V7版本开机出现 202 错误。我没能通过修改 PLD 文件消除 202 错误，用 V9 版本可以正常测量。希望wanghar把 V0.71 版本 PLD 文件发布出来进行一下参考。
3.我用双触发器没有成功，直接开机报 202 错误。
4.GPIB 采集问题：我用NI的PCI卡和 Agilent 82357B 进行采集，表量程设为10V，开启后10NPLC表底数增加2μV左右，5NPLC增加4μV左右，2NPLC增加10μV左右，1NPLC增加20μV左右，20NPLC以上看不出有任何变化。
我用34401A测试发现GPIB采集时，VDD电压增加200μV，关闭采集，在NPLC逐步增加时，VDD电压也会增加。原装U180未测试是否有此现象。
5.我自己设计布局的PCB，零点和线性度还可以，就是因为GPIB采集问题没有进行长时间采集。

我自己设计的板子，有很多错误，反相器使用了错误的封装，RUSN、LADSN、ZERO模拟开关供电都使用了VDD2 ，经过切割PCB连接到VDD。

还有我设计的 ATDH1150USB JTAG编程器也有问题：VPP12V供电采用自动供电编程时不能正常工作，所以修改了VPP12V操作方式，改为手动开关控制VPP12V电压输出。
ATMISP v7.3在解除JTAG保护时必须先接通VPP12V在执行擦写操作，擦写完成后关闭VPP12V后才能进行编程操作。
我也会更新一下我前面发出的ATDH1150USB JTAG编程器电路图。

Hello everyone,
I designed a customized version referring mainly to Wanghar’s V0.71 documents, and also fabricated a board using Wanghar’s V0.71 Gerber files.
In my self-designed version, I re-routed the analog switches and CPLD circuits. I adopted SN74AHC273 dual flip-flops and SN74LVC1G14 inverters, and added pull-down resistors and series resistors at flip-flop output ports. I revised and tested the PLD files released by MiDi accordingly.
Here are the issues I encountered:
Which firmware version of the 3458A multimeter was used in your tests? My unit reports Error 202 and fails measurement with V7 firmware. I flashed M27C4002 chip to V9 firmware, and Error 202 disappeared while occasional Error 114 occurred. After modifying the PLD program, stable measurement without Error 114 is achieved.
Without access to Wanghar’s V0.71 PLD files, I wrote and tested codes based on his schematics and MiDi files. Error 202 still pops up on startup with V7 firmware, which cannot be eliminated via PLD revision. Measurements work properly under V9 firmware. It would be appreciated if Wanghar could release the V0.71 PLD files for reference.
The dual flip-flop circuit failed to work, triggering Error 202 immediately after power-on.
GPIB data acquisition issues: Tests were conducted with NI PCI card and Agilent 82357B. With the meter set to 10V range, the reading baseline rises by approximately 2μV at 10 NPLC, 4μV at 5 NPLC, 10μV at 2 NPLC and 20μV at 1 NPLC. No obvious variation is observed above 20 NPLC.
Tested with 34401A, VDD voltage rises by 200μV during GPIB acquisition. The voltage also climbs gradually as NPLC increases after stopping acquisition. No test has been done on the original U180 module for this phenomenon.
My custom PCB delivers decent zero offset and linearity performance. Long-term data logging is suspended due to the GPIB acquisition anomaly.
Defects exist in my PCB design. Incorrect package was chosen for inverters. Power supply for RUSN, LADSN and ZERO analog switches was originally connected to VDD2, and I corrected the wiring to VDD by cutting PCB traces.
Problems also exist with my ATDH1150USB JTAG programmer. Automatic 12V VPP power supply fails during programming. I adjusted the control mode and switched to manual switch control for VPP 12V output.
When unlocking JTAG protection via ATMISP v7.3, 12V VPP must be enabled prior to erasure and writing. Programming can only proceed after disabling VPP power once erasure finishes.
I will update the schematic diagram of the ATDH1150USB JTAG programmer I shared earlier.

[DB4UCH]

Great work hanzhu!

Which firmware version of the 3458A multimeter was used in your tests? My unit reports Error 202 and fails measurement with V7 firmware.

I use v9 (and I can't really downgrade to a lower version as I have the second newest CPU board (already with a FPGA and SnapHats for the memories.))
Afaik there also exist two different FW variants for the A3 board, and the newer A3 FW only works with v8 or v9 (I don't know from the top of my head).

GPIB data acquisition issues: Tests were conducted with NI PCI card and Agilent 82357B. With the meter set to 10V range, the reading baseline rises by approximately 2μV at 10 NPLC, 4μV at 5 NPLC, 10μV at 2 NPLC and 20μV at 1 NPLC. No obvious variation is observed above 20 NPLC.
Tested with 34401A, VDD voltage rises by 200μV during GPIB acquisition. The voltage also climbs gradually as NPLC increases after stopping acquisition. No test has been done on the original U180 module for this phenomenon.

The fact that the reading baseline / zero-point changes dependent on the NPLCs is a well-known problem of basically all NU180s. The origin hasn't really been found yet.
What do you mean by the rise of VDD during GPIB acquisition?

Greetings,
Simon

p.s. Yesterday I finally ordered the v0.5.1 PCBs, so I will be able to report their performance in a week or two.

[hanzhu]

GPIB采集时U180的VDD1供电电压会升高，关闭GPIB采集VDD1电压可以恢复。
关闭采集，在NPLC逐步增加时，VDD1供电电压也会增加。原装U180未测试是否有此现象。
是不是NU180供电功率要比U180高很多？
可能是因为供电电路存在电感，模拟开关或CPLD及触发器进行高速切换向滤波电容充电造成升高？

The VDD1 supply voltage of U180 rises during GPIB data acquisition, and returns to normal once GPIB acquisition is disabled.
With acquisition turned off, VDD1 voltage climbs as NPLC value increases gradually. This phenomenon has not been verified on the original U180 module.
Does NU180 consume significantly more power than U180?
The voltage rise may be caused by inductance in the power supply circuit, or high-speed switching of analog switches, CPLD and flip-flops charging filter capacitors.

有人做过V7,2版本测试吗？是不是V7,2版本驱动逻辑和V9,2版本驱动逻辑相差很多？
过两天我做一片PGA65转接板测试一下驱动逻辑有什么区别。

Has anyone conducted tests on version V7.2? Is there a significant difference in driver logic between V7.2 and V9.2?
I will make a PGA65 adapter board in a couple of days to test the discrepancies in driver logic.

[Zondar]

Hanzu:

I have not seen a measurement of U180's power consumption, nor do I know the consumption of NU180 in actual use. I'd expect NU180 to use a little more than 23 mA (so a little over 100 mW), which is what it runs while idle. That does not sound like it would be enough to cause problems, but I'd still expect U180 to use less, since it does not include logic that would use much idle power.

However, what you are describing sounds like it could be related to the mysterious differences seen between NPLC=1 vs. 10 or 100. This is certainly worthy of broader investigation.

How much are these changes, e.g. in mV? Vdd2 should be looked at too. If your board uses Vdd2 for the switch power supplies (as it should), then it's the arbiter, for example, of any on-resistance changes due to fluctuations in its voltage. At this point, Vdd1 is pretty much only going to digital logic, so it's less clear how it might affect analog performance.

[Kleinstein]

A change in the VDD to the switches could effect the ADC gain: with 80 K and 50 K resistors per switch there is an imbalance in the switch resistance contribution.
The original U180 could have a similar issue, as the input switch used the extra supply modulation. So even with ratio matching there could be a supply effect.

VDD2 comes through a diode with only a tiny 1 nF capacitor and thus is not very stable with load and temperature.
There is also the shifted GND2 that looks like it would go with VDD2.
VDD1 has rather poor decoupling towards the clock - current spikes here could cause INL issues.

The supply to the logic could still effect delays and a modulation of the delays could effect the gain and maybe INL. This would be more the faster part (e.g. 100 kHz range), not the slow part over a full conversion.