"NU180" - A U180 drop-in replacement for the 3458A.

[Zondar]

Thank you w42i. I've made plenty of boards over the years, but I would not call myself an expert on the fine-points, so those kinds of insights are valuable. Here are some more details:

The 3458A is late-80's technology, and signals from it to the NU180 board are slow by today's standards. On the board, we have an older CPLD (that we are stuck with), one inverter and one flip-flop package. Those are faster, but all have series resistors at their outputs to slow down edges if needed.

It is a 6 layer board. The stack-up looks like this:

1) Top signal metal, a mix of digital and analog signals (mostly separated), and the remainder flooded with GND.
2) Continuous (uninterrupted) GND plane, corresponding to the main "A" ground on the A3 board.
3) Mostly continuous digital Vdd plane, with one Vdd2 trace (+4.4V supply for analog switches), which I tried to route such that it does not impede anything attached to the Vdd plane - and which I might still try to move to a different plane.
4) Mostly continuous "GND2" plane (-0.6V supply for analog switches). Two other ground-like signals were routed along with one short jumper for an analog signal. I may still move one of those, "AGND3", to a different plane, since it partially gets in the way. But there's only so much flexibility left for moving things.
5) Continuous GND plane ("A" again).
6) Bottom signal metal, mostly digital with a few analog signals, flooded with GND.

I've re-arranged the above several times and never quite feel fully satisfied, but I think it's OK, and it's a decent improvement over my prior attempts.

The path-length equalization you see in the lower left is not because the signals are super fast, but are still to equalize control signal timing. They are from flip-flop outputs going to analog switch controls after passing series resistors. The matching is probably not really going to help; in fact wanghar mentioned trying this already. It was included it in case some benefit shows up after all, or at least so I don't have to wonder later whether I should have included it. GND fill was added to reduce cross-talk, but I can remove that as you suggest.

About in the middle of the board, you should see a long vertical trace that then turns left towards the bottom-left package (the flip-flop). That one comes from a relatively fast CMOS inverter, and needs to preserve minimal jitter. There's a reflection-control resistor at its source, and I have ground on both sides as well as a continuous plane directly below. I have not calculated or adjusted the impedance of that trace yet, but I suppose the usual goal is 50 Ohms.

In case you have the time and inclination to look at it a little more closely, and if you use KiCad, I'd be very happy to send you the files. Thanks again.

[w42i]

The signals of most of my designs would also be considered slow by today's standards, but I try to learn about high-speed PCB design to be prepared should the need arise. Consequently, it is best to take may comments with a grain of salt, since I'm definitely not an experienced greybeard in this topic.

PCB design is almost always a compromise. I don't know if it is more important to have better shielding (closer GND fill) or more uniform impedance (more space to GND fill) at the path-length equalization. Just wanted to point out that it can be an aspect in some designs.

Regarding the low jitter FF track:
Since you don't have a signal sink with a defined impedance, its actual impedance should not matter. Just selecting the correct value of the source termination resistor should be enough. This can also be done by measurement and trial and error. In fact, since the output impedance of logic gates is not known exactly, this may be the only practical way if a good match is required.

The trace runs below 4 components in the first third of the trace. If you are really concerned, you may consider routing around them, because their dielectric constant (or electric conductivity) also represents a discontinuity.

However, assuming an edge time of 1ns and v=0.6*c0, the edge spreads out over about 180mm on the track, much longer than the length of the discontinuity (and the track itself). Consequently, it should not have much effect. And if the time between edges is >>1ns, even multiple reflections running back and forth should have subsided before the next edge so it should only cause some static timing change and not much jitter.
These are just my guesstimates. Would love to hear if someone more experienced approves or disagrees.

Yes, I use KiCad, but I don't think I have enough time to take close enough look to provide useful input.

[Zondar]

w42i:

I like your proposal to remove the grounds around the matched traces. They are reasonably far apart from each other anyway.

The long trace is a 20 MHz clock. It would have to take a longer path, but 603's or 805's are more practical there anyway, and room can be made.

As you say, we found idiosyncratic sensitivity to the value of the series resistors (e.g. 33 or 100 Ohms) on certain control lines - especially those for the critical 80k resistors.

Thanks again.

[qzh3887896]

The version I am using is NU180V0.4.1

[aronake]

Has anybody consulted AI for ideas on further improvement and/or things to try out? Maybe even have AI to analyze the in-guard processor program code and see if that can give more ideas?

kvez just released cal-data write program is a great example of using AI as a tool.

[Zondar]

Yet another iteration:

* Changed to LT5400-1 for the -12V Sum. I have grounded the unused resistors instead of leaving them floating (is there an idea about that?).
* Changed all other U180-critical resistors to 805's, as these are a more common size. There is space for larger (or smaller) ones if desired.
* Moved the clock line from under the ladder resistors.
* For now, the serpentine's are still flooded.
* The 50 and 80k's have the option for 805's, 2512's (for bulk foil surface mount) or for through-hole bulk-foil resistors. There is room for up to 4x resistors for any of these if people prefer to double/quadruple standard resistors, but that requires a small amount of editing.

I've hesitated about the use of LT5400-6 for the +12 Sum. The resulting ratio is not the same as in the genuine U180, but I suppose this is not considered critical. I'll probably change to it too.

It's nearly finished, though I still intend to consider more aggressive power filtering options. Are there any other recommendations?

Thank you.

(Top and bottom copper shown from 6-metal board.)

[Zondar]

Another update:

* I added the LT5400-6 for the +12 Sum as other boards have used. I'm presuming that the slightly different ratio, leading to a slightly different sum vs. the genuine U180, is acceptable given the hoped-for better TCR tracking. A question: is there any reason that the left-over LT5400-1 resistors are floating, as seen in some other boards? I've grounded them.

* More tuning of traces, etc. I still haven't removed the ground fill around the serpentine traces, and may not in the end.

So now, other than any further noise suppression, it's about finished.

* For lower noise, I suggest moving to 2.7V logic for the inverter and FF. The switches will be within spec at that voltage. The inverter I specified in V0.4 was the SN74LVC1GU04, which can operate with up to 5.5V inputs at 2.7V supply voltage, so it remains OK. The FF would need to change, perhaps to the SN54LCTH574, which can operate at 2.7V with up to 5.5V inputs as well (i.e., 2.7V from the inverter and ~4V from the CPLD). The regulators would change too, naturally.

* Using a high PSSR, LDO regulator on Vdd2, e.g. from 4.4V to say 4V, may help, and I think we can afford that modest drop in voltage. It's a pity that we can't conveniently do the same for GND2. Opinions?

* Wanghar added ferrite beads, both globally and locally, in a few cases. I'm a little leery of those due to the possibility that they may actually increase ringing, but a Pi network at the supply inputs (vs. just a large ceramic) is somewhat common and might be helpful. E.g. 47 uF Tantalum -> 10 Ohm ferrite bead -> 22 uF X7R ceramic for global power inputs.

Locally for the FF and inverter, I am already using high PSSR, LDO regulators, with additional 10 and 0.1 uF capacitors. That is probably sufficient, and I'm unsure if adding ferrite beads would help any further.

For the CPLD, which is likely to be a source of noise, I suppose adding additional local bulk capacitance might help (e.g. additional local 1 and/or 10 uF ceramics). The space is tight between signal traces, but the bulk caps probably don't need to be super close to the power pins. I don't know if ferrites would help, and wanghar did not add any here.

What else could be done? I'm not an expert on the topic of noise suppression, so please offer opinions about any of the above.

Thanks.

[IanJ]

What crosses my mind looking at the tracks from the CPLD down through the resistors and off to the analogue switches.

You have grounded copper pour between the individual digital tracks to about half-way down only, then the tracks run close together.......and from there parasitic capacitance, mutual inductance could be an issue?
Might be better to continue the copper pour fingers between the individual digital tracks all the way to the analogue switch.......to minimize coupling.

Also, maybe put more stitching on those individual fingers, you have a via at the ends only, and they look quite long......this creates a little antenna/resonators.

But I guess maybe these signals don't have much of an issue......just my tuppence worth without knowing much about the NU180.
PS. I'm following on eagerly now......my U180 is definitely broken.

Ian.

[Kleinstein]

The high PSRR LDO and the ferrites are for different frequency ranges. The ferrites also would keep the interference coming from the FF or inverter away from the supply and this way the clock generator on the A3 board. Ringing can be an issue and would ideally have a resistor (like 22 ohms) in parallel to the ferrite.

I point to consider would be pull downs also for the signals from the CPLD to the FF - these would be optional to populate but be a point for the relatively slow settling that may be causing the delay/PLC dependent offset.

With the reduced voltage for the inverter, and different logic levels, a rather low voltage for a high input can cause extra supply current with many CMOS chips. Just because they accept it as valid high state this does no mean it would be a good state. Extra supply current can cause power supply modulation.

[Zondar]

Thanks Ian: I think the signals aren't really fast enough, especially after the resistors, for ~1 cm or so of extra ground to make a significant difference, but I might do that anyway after everything else is polished off.

Thanks Kleinstein: Can you be specific about the configuration you think is best for the capacitors, ferrites, etc., including the selection of the ferrite? I've seen too much conflicting advice, and AI's seem to contradict and argue with each other about what is best, e.g. Tantalum vs. ceramic vs. aluminum-polymer for the first capacitor, etc. I believe the ferrite's inductance should be selected to match the noise frequency of interest, which for us is somewhere around the 150-200 MHz range based on the rise/fall times of the inverter and FF. I agree that a small series or parallel resistor is a good idea to help prevent LC resonances actually worsening noise (plenty of debate on that too, though).

The pull-downs on the FF lines aren't needed since all the signals have to do is get above ~2.5V before the clock arrives. The speed of that rise-time (up to ~4V) is not improved by the pull-downs, since the output impedance of the CPLD's output transistors would be around two orders of magnitude lower than the ~5k pull-downs people are using. The pull-downs only start to have an impact during the last dribble of current that the transistors output as the signal reaches ~4V. They then act to prevent the n-channel pull-up transistors from falling below threshold, thus stabilizing the output beyond that more quickly than if we just let the outputs drift into the extremely high resistance sub-threshold regime. The signal is above V_IH of the FF's long before that, and after that we don't care if there is a slight drift above ~4V. Indeed, including pull-downs here will only waste power for no benefit. Do you believe this logic is wrong?

Also, the FF's, at 2.7V, should not experience higher power consumption if their inputs are at or above Vdd=2.7V, as they all would be. Before then (by Vdd-|Vth_p|), the P-channel transistors will be completely cut off, and essentially no current could flow. The only other path to additional power consumption would be via input-protection diodes, etc., but given the rating for 5.5V inputs, that shouldn't be an issue either. Again, if you believe this logic isn't correct, please elaborate.

Edit: Oh, perhaps you are worried about the switch's inputs. They are also quite happy with inputs at 2.7V even if their power supply is above that - they are explicitly designed for this. I also directly tested this using my little ADG test board, and found no notable increase in power consumption down to about 2V even on a 5V supply.

And by the way: What do you think of adding a regulator to Vdd2, e.g. 4V? We can't do that for GND2, though.

Thanks again.

[Kleinstein]

The pull downs for the FF signals will likely not be relevant, but they are still a possible source of delayed action. This can be by things like a delay in the FF that depends on the voltage at the D input or capacitive coupling from the signals to either the clock or FF outputs. It is not only the voltage that changes, bit also the impedance (it gets high impedance when creeping up well above 4 V).

I would still consider the pull-downs more important than the trace length matching.

Ideally the filtering ferrites should get higher than the parallel resistor aready well before 100 MHz - more like 1 MHz, so that in the higher frequency range one has mainly a RC type isolation and the ferrites avoid the DC voltage drop from the supply current. I am not an expert with this, but isolating impedance is kind of needed to avoid coupling via the supply, that is hard to predict. Just a decoupling capacitor and the longer traces in between is more prone to ringing and resonances than the intentionally ferrites or ferrite plus resistor.

[Zondar]

I might still add pull-downs to the FF lines for the sake of comity, but they are not needed, and if anything would just add noise by wastefully switching mA's of power. I don't believe any other boards with FF's have used them, with no issues found by their absence. The other 5 controls do have pull-down footprints, though there's no evidence that those are needed either. My recommendation would be to not use them, or to use >=100k pull-downs rather than ~5k's.

I agree that the path equalization is not likely to be of much help. It's already been tried, after all, but at least the rise/fall times should be equalized, so it's not worthless.

Looking at the various supply inputs:

Vdd1 (5V digital power): The A3 board provides 33 uF plus 0.1 uF capacitors, as is typical. The inverter and FF's follow bulk capacitance, then independent regulators which claim to provide 60 dB of power supply noise rejection, then more capacitance (10 uF + 0.1 uF), so I'd say those are taken care of. The CPLD follows the same bulk capacitance. I've added a 603 ferrite bead and another local 10 uF cap, and the local 0.1uF's on every pin remain.

Vdd2 (4.4V analog power to switches) and GND2 (-0.6 analog power to switches): The A3 board provides only minimal decoupling on these pins. The NU180 board provides two footprints for bulk capacitance and local 0.1 uF caps directly on all switch power pins (VDD2 and GND2). The switches use very little power, with minimal di/dt (internal switching only), and so I think that should do.

AGND1, AGND2, AGND3: The A3 board includes an inductor between AGND1 and 2 and "A2," and AGND3 is connected straight to A2. "A2" is shorted to the main ground "A" on the A3 board. I have bulk capacitors to "GND" on all three. It's not absolutely clear to me that these should be decoupled to "GND" - opinions? They can always be left out if that turns out to be better.

I'll probably declare it "finished" by tomorrow.

[Zondar]

Yet more changes:

* I caved-in and added optional pull-downs on the CPLD -> FF lines. 
* I added ferrite beads to the power input path for all digital components.
* Many more minor layout tweaks.
* I spent a lot of time cleaning up the schematic for correctness and readability.

Is anything missing? I think this design includes all the ideas and features that people have concluded are important, plus some that haven't quite been proven to help but are seen as good practice to include anyway. Aside from a brilliant insight conquering the zero-point / NPLC puzzle, or ever more subtle noise reduction steps, we might be approaching a limit on this basic design.

Thus, 10 months since the project started, perhaps we have finally reached "V.1.0"?

Thank you.

[IanJ]

Thus, 10 months since the project started, perhaps we have finally reached "V.1.0"?

Patiently waiting.....JLCPCB primed....:-)

Ian.

[Zondar]

I've posted KiCad files for "V.1.0" at the bottom of the first post in this thread.

Please report any errors or omissions.

Thank you.

[IanJ]

For the low TCR 50k & 80k resistors, what is the tolerance requirement?

Ian

[Zondar]

As good as you can find and afford. The ones I used were 0.01% and 0.2 ppm.

[Kleinstein]

The TC for the 50 K resistors would effect the power effect to nonlinearity. Changes one would want better than some 2-5 ppm/K depending on the power rating. The matching bettween the 50 K to 80 K TC would be part of the gain TC.

The 50 K resistors need to be low TC, but the tolerance is not critical (1% and likely even 2% would be OK, but it adds to ref. voltage tolerance).
The 80 K reistors should be relatively accurate. They would effect the DNL via the ratio to the fine slope. AFAIR the limit should be in the 0.02% range for good DNL already with 1 PLC. The 10 PLC case would be less critical.
If really needed one could use trim (e.g. for the 5 V or at the ladder). This would include the 12 V to 5 V step and the 80 K to ladder part ratio. The 20 K to 80 K ratio would mater for the high speed mode DNL.

[Zondar]

Aside from the role that the LT5400's play, here is what I used for test boards:

50k: 0.01%, 2 ppm/C
80k: 0.1%, 10 ppm/C (best available)
20k: 0.01%, 2 ppm/C
10k: 0.01%, 2 ppm/C
24k: 0.05%, 10 ppm/C
37.4: 0.1%, 10 ppm/C
16.7: 0.1%, 25 ppm/C

The 80k's are a special problem that has haunted the project. Not only are they arguably the most important, but they are the most difficult to obtain highly spec'd. Ultimately, I bought custom-made 80k's plus a matching 50k (all 0.01%, 0.2 ppm) from texascomponents.com for U.S. $25 each. I don't know if they ship overseas, though.

Wanghar and others have found high-spec leaded 80k's on the usual-suspect sites - used pulls - for ~$3 each. If still available, that might be worth a try.

[IanJ]

Zondar, could you provide a download link to the CPLD code. I seem to have the code for 0.4.2 but not sure if V.1.0 requires updated code.

PS. my parts & Pcb on order.....:-)

Thanks,

Ian.

[Zondar]

Zondar, could you provide a download link to the CPLD code. I seem to have the code for 0.4.2 but not sure if V.1.0 requires updated code.

Many of the pins that the CPLD uses were changed to rationalize them (avoiding rat's nests of jumpers), and thus the CPLD file needs to change. I updated MiDi's file with the pin changes. Note that this file still latches all outputs, whether to the FF or not, which may or may not be correct. I can't access my latest version at the moment to check. I think DB4UCH tried both ways, so he would know. Anyway, the file is untested thus far, and may need to be modified further.

I added it to the bottom of the first post. You have to change the extension to ".pld" (can't upload a file of that type here).

[IanJ]

Zondar, could you provide a download link to the CPLD code. I seem to have the code for 0.4.2 but not sure if V.1.0 requires updated code.

Many of the pins that the CPLD uses were changed to rationalize them (avoiding rat's nests of jumpers), and thus the CPLD file needs to change. I updated MiDi's file with the pin changes. Note that this file still latches all outputs, whether to the FF or not, which may or may not be correct. I can't access my latest version at the moment to check. I think DB4UCH tried both ways, so he would know. Anyway, the file is untested thus far, and may need to be modified further.

I added it to the bottom of the first post. You have to change the extension to ".pld" (can't upload a file of that type here).

No worries, I am still a week away from assembling my board, so I'll keep my eye on a revised V.1.0 .pld source code.
I have managed to compile it successfully to a .jed file for uploading - I am using WinCUPLII on Win11 and a ATDH1150USB Microchip Programmer.

Ian.

[StacysMom]

Zondar,

I have created a Pull request for the public github repository to better reflect the current state of the project. Feel free to reach out if you have any questions or if you feel any changes should be made.

Thanks,

Tim M

[Zondar]

I have created a Pull request for the public github repository to better reflect the current state of the project.

As I have barely used github, I'm afraid that I don't quite understand this. Which public repository? Are you requesting action on my part?

Thanks.

[MiDi]

https://github.com/NuZondar/NU180