"NU180" - A U180 drop-in replacement for the 3458A.

[Zondar]

I've updated the github files for V.1.0.:

https://github.com/NuZondar/NU180

Edit: I updated the CPLD code to remove CPLD-level latching of the FF signals. I haven't tested this, but I believe this should be correct.

[IanJ]

I've updated the github files for V.1.0.:
https://github.com/NuZondar/NU180
Edit: I updated the CPLD code to remove CPLD-level latching of the FF signals. I haven't tested this, but I believe this should be correct.

I tried compiling this new code but it fails (WinCUPL II), but the previous version was fine.
Looking at the code, I had to change the following which I believe is wrong for “unlatched/combinational” outputs. It looks like the equations were still left as .D equations.

Code: [Select]

NS2.D    = ENS & !SLB;
NR2.D    = ENR & !SLB;
NS1.D    = ENS & !SLA;
NR1.D    = ENR & !SLA;
PS2.D    = ENS & SLB;
PR2.D    = ENR & SLB;
PS1.D    = ENS & SLA;
PR1.D    = ENR & SLA;
To:

Code: [Select]

NS2      = ENS & !SLB;
NR2      = ENR & !SLB;
NS1      = ENS & !SLA;
NR1      = ENR & !SLA;
PS2      = ENS & SLB;
PR2      = ENR & SLB;
PS1      = ENS & SLA;
PR1      = ENR & SLA;
I'm not that experienced in CPLD.....it's been many years!......hope the above is correct?

Ian.

[Zondar]

Ian:

Yes, that's looks right. I corrected the version on github and on the first post of this thread. Thanks for pointing out the error.

[IanJ]

My V.1.0 Pcb's have arrived.
I have all the parts........so let the fun begin!

Ps. It's my own modified version of Zondar's V.1.0, specifically around the 50k/80k resistors.

Ian.

[IanJ]

Hi all,

Finally got my NU180 assembled, programmed and first power up.
Zondar's V.1.0 Pcb slightly modded just to accommodate my own initial 50k/80k resistor setup.
Single 50k, and 2off 40k's in series to get 80k. All low TCR 0.2ppm/degC / 0.01%

Using the latest unlatched CPLD code.

CPLD programmed before power up on the A3 board.

5v & 3.3v are good.
JP1 & JP2 set to 5v position (tried 3.3v position also)
No 100k pulldowns (13off) fitted.

+/-12 Ref are ok
PIN16 +5REF = 5v
RN1 +12SUM = +7.18v
RN2 -12SUM = 0v

3458A error on boot 202 - Slave Test Convergence.
Display blank (as it was with U180).
If I then TARM AUTO as I did with the U180 instead of getting data I get an error 114 - balanced rundown convergence.

All soldering/reflow is fine.

So, just wondering what are the things to check first?

PS. I do have another drifty A3 board I can try it on, which does actually power up with data on display rather than requiring setting TARM AUTO to get it going.

Thanks,

Ian.

[Kleinstein]

Some of the boards have problems with the fine run-down. E.g. from extra delays or an error (e.g. effset from resistor values that are a bit off) in the ladder part. One should see this at the waveform for the integrator or slope amplifier output (TP112, TP140).
Some boards want an extra capacitor to speed up the slope amplifier.

[IanJ]

Tried the other A3, same symptoms……so that’s good news, I can look at the NU180 in more detail.
Just wondering if there are waveforms etc posted on this thread I can look at and compare.

Might also double check CPLD code/programming as I don’t think anyone else has used my toolchain.

Ian

[Kleinstein]

Waveforms to compare too are here:
https://www.eevblog.com/forum/metrology/nu180-a-u180-drop-in-project-for-the-3468a-dvm/msg6089809/#msg6089809
https://www.eevblog.com/forum/metrology/so-i-have-a-mint-condition-agilent-3458a/msg6046739/#msg6046739
and a few responsed around.

[IanJ]

Zondar,

Could you check the V.1.0 CPLD code, I think there might be some pin mapping errors. The V.1.0 Pcb doesn't seem to match the CPLD code........if I am reading this correctly.

I noticed pin 19 on the Pcb CPLD is grounded, but it's referenced in the code
PIN 19       = PS2;                         /* S8:  30 positive RU speed ref2  */

So, I started looking at the others.

Original V.1.0 code:

Code: [Select]

/* *************** INPUT PINS ******************** */
PIN 23       = ENR;                         /*                                 */
PIN 27       = ENS;                         /*                                 */
PIN 33       = SLA;                         /*                                 */
PIN 31       = SLB;                         /*                                 */
PIN 25       = RUR;                         /*                                 */
PIN 30       = RUZ;                         /*                                 */
PIN 28       = RUS;                         /*                                 */
PIN 37       = CLK;                         /* GCLK1                           */

/* *************** OUTPUT PINS ******************** */
PIN 34       = RUSN3;                       /* S0:  13 AC_AD                   */
PIN 14       = RUSN2;                       /* S1:  14 AGND                    */
PIN 35       = RUSN1;                       /* S2:  18 DC_AD                   */
PIN 15       = LADSN;                       /* S3:  15 rundown ladder sum node */
PIN 21       = NS2;                         /* S4:  23 negative RU speed ref2  */
PIN 22       = NR2;                         /* S5:  22 negative RU resol ref2  */
PIN 12       = NS1;                         /* S6:  21 negative RU speed ref1  */
PIN 13       = NR1;                         /* S7:  27 negative RU resol ref1  */
PIN 19       = PS2;                         /* S8:  30 positive RU speed ref2  */
PIN 18       = PR2;                         /* S9:  25 positive RU resol ref2  */
PIN 11       = PS1;                         /* S10: 28 positive RU speed ref1  */
PIN 10       = PR1;                         /* S11: 31 positive RU resol ref1  */
PIN 20       = ZERO;                        /* S17: 20 zero integrator         */
/* PIN        = NENR;                       /* inverted ENR - not connected    */
/* PIN        = NENS;                       /* inverted ENS - not connected    */
My suggestions for remap:

Code: [Select]

/* *************** INPUT PINS ******************** */
PIN 2        = ENS;       /* U180 pin 46 */
PIN 3        = RUZ;       /* U180 pin 44 */
PIN 6        = SLB;       /* U180 pin 42 */
PIN 8        = SLA;       /* U180 pin 40 */
PIN 10       = ENR;       /* U180 pin 47 */
PIN 11       = RUR;       /* U180 pin 45 */
PIN 12       = RUS;       /* U180 pin 43 */
PIN 37       = CLK;       /* XCK20, U180 pin 33 */

/* *************** OUTPUT PINS ******************** */
/* Direct registered outputs */

PIN 13       = RUSN3;     /* S0  */
PIN 14       = RUSN2;     /* S1  */
PIN 15       = RUSN1;     /* S2  */
PIN 20       = LADSN;     /* S3  */
PIN 18       = ZERO;      /* S17 */

/* Combinational outputs feeding U10 SN54LVTH574 */

PIN 21       = NR2;       /* U10 D0 -> Q0 -> S5  */
PIN 22       = NS2;       /* U10 D1 -> Q1 -> S4  */
PIN 23       = PR2;       /* U10 D2 -> Q2 -> S9  */
PIN 25       = PS2;       /* U10 D3 -> Q3 -> S8  */
PIN 27       = NR1;       /* U10 D4 -> Q4 -> S7  */
PIN 28       = NS1;       /* U10 D5 -> Q5 -> S6  */
PIN 30       = PS1;       /* U10 D6 -> Q6 -> S10 */
PIN 31       = PR1;       /* U10 D7 -> Q7 -> S11 */
Again, I am no CPLD expert but if you could check then much appreciated.

I tried the above but still not working so no idea if there are other code issues, or if I've got it wrong.

Ian.

[MiDi]

If you have working drifty A3 then just swap U180 and check.
You can measure ref resistors to check the ratios on desoldered U180 to make sure those are the culprit.

The CPLD code is as easy as it can get, just check input and output pins in code match with your NU180 schematic.

[IanJ]

Ok, I got the NU180 working.
Some more mods to the pin assignments to match Zondar's V.1.0 Pcb.
Attached.

Now I can do some real testing.

Ian.

[Zondar]

The code I provided was untested (I don't yet have my own board). I don't know how things got so scrambled (sorry), but here's the map I see:

S0 -> Pin 13
S1 -> Pin 14
S2 -> Pin 15
S3 -> Pin 20
S4 -> Pin 21
S5 -> Pin 22
S6 -> Pin 28
S7 -> Pin 27
S8 -> Pin 25
S9 -> Pin 23
S10 -> Pin 31
S11 -> Pin 30
S17 -> Pin 18

By the way, I'm curious about which resistors you used for the 50 and 40's.

[IanJ]

I am using 0.2ppm/degC 0.01%

Y407550K0000T9R
SMD Chip Resistor, Flip Chip, 50 kohm, ± 0.01%, 500 mW, 2010 [5025 Metric], Metal Foil
Manufacturer:
VPG FOIL RESISTORS
Farnell Order Code - 4016010

Y407540K0000T9R
SMD Chip Resistor, Flip Chip, 40 kohm, ± 0.01%, 500 mW, 2010 [5025 Metric], Metal Foil
Manufacturer:
VPG FOIL RESISTORS
Farnell Order Code - 4016007

It's just a single 50K, but I have spares so plan is to use 4off 50k to make 50k......I can hack this on easily. Two parallel pairs in series, this spreads the power dissipation across four components, reducing self-heating and improving thermal stability compared to a single 50k resistor

2off 40k in series to get the 80k.

They are expensive!

Ian.

[Zondar]

Ian privately pointed out to me that V1.0 had grown large enough that one corner (lower right) can interfere with one of the optical connectors on A3. Therefore, V1.1, with a cut on that corner, is in-progress, and a prototype is shown below.

At this point, I'm not sure that a new breakthrough improvement in noise or linearity, etc., will be forthcoming. That would be great, and speak up if you have made one, but it's more likely that further improvements will be smaller and incremental in nature. Therefore, I'm making a few other more subtle changes:

* An attempt to insure that all analog traces are on the top copper only (no jumpers at all anymore if possible).
* Reconsider the stackup again, as I think that can still be improved, for example to lessen the need for a thin stackup (as was preferable for V1.0).
* I'm considering partially or fully removing the flood on the top copper as being potentially more trouble than it's worth. Since I had made enough room between traces for a copper pour, the spacing is already large enough to minimize cross-coupling anyway.
* I'll probably include the high-voltage CPLD reprogramming pin that wanghar had on one of his boards as a "just in case" feature.
* I may remove the optional 805 footprints on the 50 and 80k's. It's clear that utmost-performance resistors are needed here, and no 805's will cut it. If a low-cost prototype is desired, the through-hole footprints can be used, e.g. with good quality metal film resistors.
* Some other more-critical resistors like the 20k's may be better off in 1206-size.
* Go back to part numbers on the silkscreen instead of part values.
* Some more never-ending cleanup and detailing.

If there are any thoughts, concerns, or other ideas for changes and improvements, please let me know. Otherwise, I'll likely have V.1.1 finished in a few days.

Thank you.

[Zondar]

About the intertwined + and - slopes per switch package that boards have moved to (vs. my earliest approach). MiDi's explanation was:

"The reason for the interdigitized switch arrangement was simply to get a better balance/cancellation between + and - slopes with no downsides and easy to implement - but would not overestimate the effect." (Post 58)

There is a down-side, though. To intertwine them per switch package, there is no alternative but to use at least one and more likely two jumpers - on the analog signals - between the pins and switch packages. On the other hand, if one package handles the +12 and one the -12, there is no need for this, and the layout is much cleaner over-all.

Though early results seemed to indicate it's better, those results were made while many things were still being changed. Are there any more recent thoughts about this, or is it certain that it's worth the cost?

Thanks.

[Kleinstein]

Mixing the +12 and-12 V per chip would give slightly better matching of the R_on. However I would not expect a large effect: the switch resistance is rather low anyway and the switch chips are likely from the same batch, which lets us expect also OK matching between chips. I would prefer a cleaner layout with less parasitic capacitance and coupling from the control signals to the switched signals.

[MiDi]

Changing the switches at least for the +-12V slow slopes (80k) might be worth a try.
Currently the switches have dual supplies, which indicates that there is additional level shifting of the digital input which might introduce additional jitter.
ADG772 looks like a good balanced switch for this application, downside is 3.3V only and tiny package.

In general reducing the stray capacitance to a minimum at the switches and the corresponding connection to the resistors sounds like a good idea, especially to the 80k.
To reduce stray capacitance to the ladder resistors the pins 17, 20 & 22 could be removed.

[Kleinstein]

The stray capacitance at the ladder should not be so bad. There is already resistance to ground at the integrator input.
Parasitic capacitance to the control lines can be an issue.
The other point, where capacitance matters is at the points where the reference resistors connect to the switch. That part pumps charge out, if the integrator is not perfectly at ground and the reset charge adds noise.

[Zondar]

OK, I've changed back to +12 and -12 on separate packages. This requires another set of simple changes to the CPLD program regarding which pin is which. Personally, I don't think this change is much of a risk. As a result, all related analog signals are now on top-metal only - no jumpers. It's significantly cleaner.

I looked at the ADG772. It is targeted at digital applications (e.g. USB) rather than analog ones. It's interesting, but it would pose a few problems for us. For one, there's no negative supply, so GND2 can't be used. As Kleinstein points out, that is not necessarily terrible, but I do think it's preferred to keep the use of GND2. We would also need to regulate Vdd or Vdd2 down to 3.3V. It has over 2x the on-resistance and its resistance is much less flat (the latter is also not super important, but doubling the resistance certainly isn't good).

It's fair to speculate that it may show less jitter (it indeed may), but we lack actual knowledge in the absence of specs or measurements. It could be worth a try but, given the down-sides, including that it turns out obviously worse (for example, two of us failed to get the TMUX's working at all), I'd prefer to stick with the proven switches for now.

I changed the 20k's, the last 10k, and the 24k to 1206's. This allows choosing bulk-foils for these as well if desired or found necessary. Otherwise, there's extra room to change the footprints to smaller ones.

There are a few more tweaks I still need to make:

* Add the high voltage CPLD reset pin.
* I'm still debating whether to remove the flood on the top metal, and maybe a few of the others.
* I'm probably going to move the CPLD to FF traces to the bottom metal.
* I still think the stack-up can be improved.
* More endless cleaning-up and refining.

[Kleinstein]

The ground fill on top can make sense to reduce coupling capacitance. This would be especially between the control and analog part, but also between digital signals (capacitive coupling to a variable impedance node gives variations in the delay). In most combinations it would still not matter.

The resistance flatness of the switches does not matter. The switches are used at an essentially fixed voltage, some +-10 mV GND. Also leakage current should be not that relevant, as the switches see low voltage across and leakage would only result in an offset. The relevant parameters are charge injection (switches at GND), the capacitance and jitter.
For the 80 K ref. switches a slightly higher on resistance should not be an issue. It can be for the 10 K input (AC mode) and 20 K paths.

[Zondar]

The contemporary thought about flooding with ground is that it can help lower cross-talk, but also it risks backfiring if not executed properly. A commenter in this thread made that point earlier.

KiCad prevents floating ground fills. However, it doesn't care if that fill is grounded at a single point, or multiple, or where or how far apart the connections are, etc. If those connections are inadequately spaced, e.g. if they are farther apart than say half the wavelength of an attacking signal, then the "ground" fill is inadequate and will transfer a significant amount of energy to a victim trace.

For example, between the CPLD and FF's, I have fill between the traces, with connection to ground at the top and bottom of the fill. But do I need more in-between? KiCad offers no help here.

On the other hand, by simply spacing the signals far enough apart the risk of cross-talk is already very low - with no risk that an inadequate "ground" fill will act as a transferring intermediary.

Since I'm not a layout super-expert, I'll probably take the path of least resistance (hehe) and leave the fill as-is. 

Also: An asymmetry in resistance, even a very small one, could possibly still matter. We do seem to see a small but consistent performance asymmetry in one or two figures of merit, including one that apparently grows as NPLC grows, and yet we don't know what is causing it. I suggest we don't want to move to a switch with a higher R_ON asymmetry unless there's a clear overriding benefit.

[Kleinstein]

For testing switches for jitter my AVR based ADC board (or a related board version) is probably better suited.
https://www.eevblog.com/forum/metrology/diy-high-resolution-multi-slope-converter/msg6316302/#msg6316302
One has the freedom to change how fast the modulation run's and this way tell apart noises sources somewhat: the noise from jitter and the switch capacitance goes up with the switching frequency. Amplifier and resistor noise would not change with the frequency.

[Zondar]

I've revised the layout to try to put all of the analog signals on the top copper only, with zero jumpers, directly over a continuous ground plane. There is only one remaining exception, the Pin 54/55 Sum 1+2, which can't be routed there without interfering with too much other stuff. That's presently on the bottom copper, and it's OK there, as it's completely surrounded by GND, but I may move it to an interior ground plane.

I've also pushed all longer digital traces to the bottom copper. The only exception is the clock line, as I'd prefer not to use vias for that. On the other hand, it looks wrong on the top copper. Are there any opinions about this?

Some further thoughts:

* The board includes both through-hole and surface-mount footprints for the 50 and 80k's in the hopes that it would provide flexibility. However, if custom resistors really are needed for this (at least the 80's, anyway), how useful is this? My supplier for custom values charges the same for either. Wanghar, at least, found inexpensive through-hole bulk-foil 80's. Anyway, the layout would be more efficient if, say, only through-hole positions were provided. I sometimes think through-hole versions may be a better choice anyway, e.g. in case you need to move them between boards.

It may be that there is no one good solution, and in that case leaving the room for others to edit the layout to suit their needs might be best in the end (there's ample room at present). For example, Ian is using 2x40k resistors for each 80k, which is an expensive option, but at least with some limited off-the-shelf availability. Opinions?

* I'd love to put the CPLD and its resistors on the back side of the board. However, I think this would cause big problems for many builders, including myself.

A few problems have arisen:

* I'd like to improve the stack-up by swapping the digital power plane for one of the analog ground planes. I can't figure out how to do this, except perhaps by editing the raw text of the layout or redoing layers from scratch. There is a "swap layers" dialog box (KiCad 9.0), but I can only select one side (one layer on left or right side), so it seems to do nothing. I even added a new blank layer as a temporary target, but that doesn't help either. Any ideas?

* I had a new error appear that I can't seem to get rid of. It claims that the top copper fill is not connected to the top copper fill (i.e., itself). I've deleted it, redrawn it, and tried a few AI-hallucinated ideas, and the error remains. Any clues?

Here's the top-copper only for clarity.

[MiDi]

There are a lot of comments on your design, maybe worth to look back at them (e.g. low stray capacitance)
Would not recommend to put components on the bottom layer unless needed, makes things more complicated to solder and may interfere with components on A3 (e.g. in my design the CPLD sits at the bottom inside the socket).

Edit: just another general thing that came to mind, before I forget about it: the charge injection from the zeroing of the integrator could add additional noise (INL?), not only the 80k switches

[DB4UCH]

* I had a new error appear that I can't seem to get rid of. It claims that the top copper fill is not connected to the top copper fill (i.e., itself). I've deleted it, redrawn it, and tried a few AI-hallucinated ideas, and the error remains. Any clues?

Here’s your issue (marked in the picture)

As for the other things, I didn't really have much time the last few months, so I didn't follow the thread too much nor did anything with my 3458A, although I think I will build the v1 after it's been released.

Greetings,
Simon