ADR1001 - Ovenized Voltage Reference System

[Andreas]

More specifically, how does the long-term stability of the ADR1001 5 V reference compare to that of an average LM399 or ADR1399 7 V reference?

Hello,

sorry, but I have monitoried only 1 sample of ADR1001 for 3 kHrs.
So it is too early to judge over ADR1001.

And then the individual devices behave very different (e.g. popcorn noise)
-> for high demands you have to select the best out of a bunch of samples.

Generally up to now I would prefer a metal can package over a SMD ceramic package to keep influence from PCB away from the chip.

with best regards

Andreas

[FriedLogic]

Has anyone tested the demo board (or their own version) to see how much the ADR1001 is actually affected by humidity on an FR4 PCB?

I know that a flex PCB is one option, but I would like something a bit more rigid. I did see the version that Marco Reps made.
Something like the ZYF255DA PTFE/glassfibre material from JLCPCB looks interesting.

Thanks.

[Andreas]

Hello,

I passed 4kHrs of my ADR1001 eval board on 5V output.

see 3kHr measurement before:
https://www.eevblog.com/forum/metrology/adr1001-ovenized-voltage-reference-system/msg6036683/#msg6036683

It needed around 1kHr to get back to the same level as before the 1 week power off. (see zoomed diagram).

with best regards

Andreas

[iMo]

I made some small changes in myADR1001#1 (now #1B) 10V reference:

1. added 100nF (wima) foil into the feedback of the internal output buffer (as per 10V DS schematics)
2. increased the fb capacitor in the OPA189's output buffer from 4n7 to 100nF (wima)
3. added 4u7 tantalum drop at the 10V output
4. shortened the legs of the carrier/bobin (a 39k 2W resistor) of the wirewound IZset resistor by aprox 5mm at each side (and soldered back)
5. replaced the rather dense foam insulation with 1cm thick styrofoam plates creating an internal box.

The 1.-3. changes were focused on increasing the stability. Below a FRA simulation of the output OPA189 buffer made with the TI's model (rather large model, indeed, you have to fix the symbol's pin assignments of the LTspice opamp in order to get it working properly).
The above changes have increased the output voltage by aprox 4-6uV.

Below you may find an example of using myADR1001#1B as the 10V voltage reference for the "ratio measurement" of an LT1021 plastic sample (via HP34401A). The voltage of the plastic LT1021 is still slowly dropping after 4 days of its power on, btw..
The ratio measurement made at 10NPLC with subsequent median and TEMA smoothing seems to me one of the best options here as it helps to eliminate HP's 399 rather large 1/f and occasional pops, as well as the HP's TC. The TC of the ADR is included into the process as well.
This may somehow indicate the limits of the 34401A for "direct measurements inside its 10uV resolution" (at the 10V DC range).

[exe]

The above changes have increased the output voltage by aprox 4-6uV.

Apologies, I'm noob, but why capacitors would increase voltage?

[iMo]

Added point 4 - the legs of the carrier resistor on which the wirewound zener's current setting resistor is wound were shortened by aprox 5mm at each side (was 10-12mm). That change may contribute to the voltage rise as well (the sensitivity there is aprox -250uV/ohm change at the 10V out), but I doubt the resistance change was so large.
The influence of capacitor's values changes at the output voltage has been always visible there in my case, as I can remember from past. The capacitors even the foil one may introduce a leakage, for example.. And the opapm there is a chopper, so perhaps the capacitors around the opamp may shift the average value of the spikes..

[MiDi]

OPA189 offset voltage is known to be sensitive against input impedance: https://www.eevblog.com/forum/metrology/emi-measurements-of-a-volt-nut/msg2824498/#msg2824498 and next post.

[iMo]

Yep, and that is the reason I put the 1k resistor into the OPA189's IN+ input..
This time the change has been with C5 above (from 4n7 to 100nF).

[miro123]

1. Can ADR1001 out directly power such huge capacitive load?
2. I am not a big fan of such asymetric output.
   - almost zero impedance by sourcing current, and 10k sinking
   - modern TI opamas including zerodrifts opa18x offer decent protection, load capability including power rails and protections.
3. FRA tells 20..25% of the story. Many transient analysis must check the the reaal life situation - e.g. over current and recovery after, sink 65ma and recover after. Why 65ma - because the naked OPa189 has such protection in output stage.

[iMo]

When you open the ADR1001's datasheet the first picture there shows "1uF to 100uF" capacitor at the output of its internal buffer..

1. Can ADR1001 out directly power such huge capacitive load?

2. yep, we had a discussion on it, afaik.. My output buffer is the 3y old design from the beginning of this thread, intended for light loads like an input of a DMM. When driving the heavier loads the symmetric output would be the way to go (ie. there some sims with OPA/ADA as the first low drift opamp and a NE5xxx as the "power output" within the OPA/ADA's loop).

PS: for example OPA189 and NE5531

[Andreas]

Hello,

I passed 5kHrs of my ADR1001 eval board on 5V output.

Ageing drift is now within measurement noise level. -> I need longer observation time.

with best regards

Andreas

[iMo]

..it looks like your adr1001_1 has smaller fluctuations than the LTZ#9.. (provided the measurement process is the same)..

[Andreas]

Hello,

what makes you think to have smaller fluctuations?

when I look at the standard deviation over 42 days (1000 hours) both are near 0.075 ppm which is determined by my measurement setup.
(Averaging 2 DMMs and 3 of my ADCs)
The only difference between ADR1001 and LTZ#9 is the input channel of the relay multiplexer.

with best regards

Andreas

[iMo]

..last ~35days the adr1001_01 has got lower stddev in average.. 

[Andreas]

Hello,

I passed 6kHrs of my ADR1001 eval board on 5V output.
Maybe that the last "kink" some days before has occurred due to weak battery supply.

with best regards

Andreas

[Andreas]

Hello,

I passed 7kHrs of my ADR1001 eval board on 5V output.
The measurements which are relative to my most stable reference LTZ#4 seem to go slightly down on ADR1001.

In comparison to the LTZ#9 drift vs LTZ#4 there seems to be no clear winner in standard deviation over the last 42 days/1000 hours.
(its all close to my measurement setup limit).

with best regards

Andreas

[DMJ]

Thanks for your prolonged time and effort logging the ADR1001 Andreas!
Being a longtime lurker of the metrology section, I was happy enough to recently get the chance to design a 5v voltage reference.

While being somewhat scared of the initial drift, partially from the posts in this topics, I chose to go with the ADR1001 because of the MOQ of the high precision resistors needed for LTZ/ADR1000.
Now my findings are still very preliminary but i'm still somewhat surpised by them so far.

I assembled 4 prototypes, which I checked regularly over 14 days using a DMM7510.
They all seem to have a roughly equal initial drift behaviour, showing a negative drift of about 15 to 25 uV over the first 7 days and they have all been pretty much stable ever since. The plot below shows ambient temperature vs DMM7510 readings.
The DMM is used in 12 NPLC, 5 readings. In the plot the readings are averaged per hour. The gaps in the data are from having other DUTs connected, Dut wasn't turned off.

 
Now I highly doubt that I did some magic in my design that's causing this fast initial drift, so it left me wondering if there perhaps has been some change to the silicon by AD. My ADR1001's are datestamped #2523. Looking back in the thread I believe yours are early 24. Could it be a change in the newer silicon or am I just looking a an extensive mistake in my measurement setup? Anybody with a newer evaluation board perhaps?

[iMo]

Could you tell us what type of construction you have made and at what temperature you run the oven?

[Andreas]

Now I highly doubt that I did some magic in my design that's causing this fast initial drift, so it left me wondering if there perhaps has been some change to the silicon by AD. My ADR1001's are datestamped #2523. Looking back in the thread I believe yours are early 24. Could it be a change in the newer silicon or am I just looking a an extensive mistake in my measurement setup? Anybody with a newer evaluation board perhaps?

Hello,

in the ppm precision level every chip behaves rather individual.
I would blame a fast initial drift either on the die attach between chip and case
or perhaps on the heat influence on the PCB during soldering.
(The epoxy dries out and after the soldering ther is some relaxation due to environment humidity).

Of course any change or improvement at the manufacturer can also have an influence.
Although I am not aware of any PCN related to the ADR1001.

I would also monitor the humidity during the ageing measurement.
And with seasonal changes you will see the final result after minimum 1 year.

And please show photos from PCB and mounting method of the chip on the PCB.

with best regards

Andreas

[dietert1]

The graph shows that there is ambient temperature influence, but not the simple, immediate one described by the TC parameter. One can see delayed compensation, typical for a meter (more complex than a voltage reference).
Is the meter exposed to similar ambient temperature variations?
Is the meter new as well? Is it powered continously or was it turned on for this experiment?
Apart from that some ppm of initial drift is normal for a zener reference, let's say within first week.

Regards, Dieter

[branadic]

The datasheet states a typical drift of -3 ppm (15 µV for 5 V) in the first 200 hours (~8 days) and -5 ppm (25 µV for 5 V) for 1000 hours (~42 days) for the raw zener core (6.6 V).
Additional drift from the divider creating the 5 V out of the 6.6 V is to be expected as well. So besides the temperature influence, that can be seen in your graph and that dieter1 already pointed out, the drift you are seeing is not too surprising (carefully read the datasheet). Other people already pointed out before, that the divider and/or the buffer amplifier are not superior and rather noisy as well.

-branadic-

[DMJ]

Could you tell us what type of construction you have made and at what temperature you run the oven?

The construction is pretty close to the evaluation board. It's an FR4 PCB with cutouts around the ADR1001 with some additional components, a plastic cap covering that section and the entire PCB placed in a Hammond enclosure. Oven setpoint is 60 degC.

I would also monitor the humidity during the ageing measurement.
And with seasonal changes you will see the final result after minimum 1 year.

And please show photos from PCB and mounting method of the chip on the PCB.

Agreed, this is still very preliminary, longer term testing will tell. Next tests steps will include climate chamber tests and switching the Duts off and back on to determine hysteresis.
Since this is a commercial project i'm afraid I can't share photos, as mentioned though, it's not that different from the evaluation board. 

The graph shows that there is ambient temperature influence, but not the simple, immediate one described by the TC parameter. One can see delayed compensation, typical for a meter (more complex than a voltage reference).
Is the meter exposed to similar ambient temperature variations?
Is the meter new as well? Is it powered continously or was it turned on for this experiment?
Apart from that some ppm of initial drift is normal for a zener reference, let's say within first week.

Regards, Dieter

I think that's hard to say from these hourly averaged plots. The reference is covered with a plastic cap and inside an aluminium enclosure, which I guess can also cause some delay.
The meter is indeed exposed to the same ambient. Meter has been in use for prolonged time and was allowed to stabilize for at least 24 hours before these tests. But here there could definitely be some drift by DMM7510 aswell to take into account.
Agreed that the initial drift is as expected, even more inline with datasheet spec than the drift of the eval board as recorded by Andreas.

The datasheet states a typical drift of -3 ppm (15 µV for 5 V) in the first 200 hours (~8 days) and -5 ppm (25 µV for 5 V) for 1000 hours (~42 days) for the raw zener core (6.6 V).
Additional drift from the divider creating the 5 V out of the 6.6 V is to be expected as well. So besides the temperature influence, that can be seen in your graph and that dieter1 already pointed out, the drift you are seeing is not too surprising (carefully read the datasheet). Other people already pointed out before, that the divider and/or the buffer amplifier are not superior and rather noisy as well.

-branadic-

Yes agreed, comparing to the datasheet the drift is not far from the typical values, looking at the plots though, f.e. plot 12, the initial drift for my 4 prototypes is below the -1 sigma line, at least on the first 150 hours. Time will have to tell if it's just faster drift or also a bigger drift.
My surprise was not so much comparing to the datasheet but more to the data of Andreas. So I guess I'm just happy that I didn't find that pretty much linear looking drift of say 4 ppm over 50 days his plot shows initially.

[CalibrationGuy]

Now I highly doubt that I did some magic in my design that's causing this fast initial drift, so it left me wondering if there perhaps has been some change to the silicon by AD. My ADR1001's are datestamped #2523. Looking back in the thread I believe yours are early 24. Could it be a change in the newer silicon or am I just looking a an extensive mistake in my measurement setup? Anybody with a newer evaluation board perhaps?

Hello,

in the ppm precision level every chip behaves rather individual.
I would blame a fast initial drift either on the die attach between chip and case
or perhaps on the heat influence on the PCB during soldering.
(The epoxy dries out and after the soldering ther is some relaxation due to environment humidity).

Of course any change or improvement at the manufacturer can also have an influence.
Although I am not aware of any PCN related to the ADR1001.

I would also monitor the humidity during the ageing measurement.
And with seasonal changes you will see the final result after minimum 1 year.

And please show photos from PCB and mounting method of the chip on the PCB.

with best regards

Andreas

"heat influence on the PCB during soldering"

This item here as Andreas pointed out has a very large influence. I've seen manufacturers heat and cool completed assemblies to relieve stress and also to root out marginal boards.

TomG.

[iMo]

FYI- After the winter sleep (aprox 6 months) I fired up both myADR1001#1 and 34401A. I let them settle for 1 week, and below the 13h long overnight measurement (100NPLC).
The TC of the ADR is not incorporated into my DMM TC compensation, with ADR's aprox -0.144ppm/C you may subtract say 2-3uV.
The last measurement in 2025 at 23C was 9.999.894V.
Disclaimer: this is not metrology grade measurement.

[Andreas]

Hello,
more interesting would have been the behaviour during the 1 week stabilisation with your spider web design.
with best regards

Andreas