What's the noise performance wrt to the "normal" grounded configuration?
Hi mawyatt,
That is a crucial question. Mathematically, since we have multiple op-amps wrapped into interlocking feedback loops, their individual noise contributions add up orthogonally (as the root of the sum of squares).
In a standard single-ended configuration (Zener anode tied straight to hard ground), the output noise floor is determined by the Zener itself plus just one scaling/buffer op-amp.
In this floating core topology, the noise is slightly higher on paper because three op-amps (U4, U6, and U8) actively manage the biasing and potential translation with an error transfer coefficient of 1.44 each. The current-source op-amp (U3) is mathematically heavily attenuated (by a factor of ~0.00022 due to the R9/rz ratio), so its noise contribution is virtually zero.
However, in practical terms, this does not become a bottleneck at the 10V output terminals across the entire technological spread of the ADR1399 silicon.
The TP27-SR op-amps used in this design with low noise floor of just 0.1 µV p-p in the 0.1–10 Hz band. When we calculate the cumulative noise contribution of all three active op-amps at the output, it scales to roughly 0.25 µV p-p.
Let's look at the final RSS-summed noise on the 10V terminals for different Zener selections:
1. For a hand-picked, "golden" Zener sample (1.0 µV p-p at the Zener level -> 1.44 µV p-p at 10V output):
V_total = sqrt(1.44² + 0.25²) ≈ 1.46 µV p-p (Actual noise penalty: ~21 nV)
2. For a typical datasheet Zener (1.4 µV p-p at the Zener level -> 2.02 µV p-p at 10V output):
V_total = sqrt(2.02² + 0.25²) ≈ 2.03 µV p-p (Actual noise penalty: ~15 nV)
3. For a worst-case datasheet Zener (2.2 µV p-p at the Zener level -> 3.17 µV p-p at 10V output):
V_total = sqrt(3.17² + 0.25²) ≈ 3.18 µV p-p (Actual noise penalty: ~10 nV)
Summary:
The total noise penalty of this multi-loop architecture compared to a standard grounded configuration is roughly 30 nV at the 10V terminals.
The baseline noise floor remains strictly limited by the physical properties of the ADR1399 silicon itself. We are essentially trading an invisible 30 nV worst-case noise penalty for improved immunity against EMI/RFI and ground loop currents.