Analog frontends for DMMs approaching 8.5 digits - Discussions

[julian1]

Ok, this looks more promising,

test15
baseline max4053, 2.7V supply. 500us precharge. 1nplc
+10V        -12mV
0V          7.0mV.
-10V        26mV.

identical - except with the azmux out pin lifted (U414,p8).
1nplc
+10V   2.6mV. 2.6mV
0V.    5.0mV. 5.0mV.
-10V.  8.5mV. 8.4mV.

No components are populated at the end of the short azmux-out trace.
So this suggests pretty strongly a layout/pcb effect - coupling, board DA, or guard or similar.
there's a lot that can improved here, but the bootin/guard is the easiest and probably should be addressed first.


Leakage may also be slightly better - suggesting pcb leakage > adg mux leakage.
perhaps still some DA mixed up in the result too, with a 5min settle-time.

leakage 1000nplc/off
+10V.  -0.2mV.
0V.     1.7mV. 1.0mV. 0.1mV.  ??
-10V    2.2mV. 2.1mV.

[julian1]

Reviewing the pcb again, and there is single control-trace for the azmux (that is used), routed about 1.27mm over the mux-output.
it is separated by fr4 core, but still a good candidate for the issue.
using a wire bodge from mux-out instead of the pc btrace should be a workaround.
Edit. now i am not sure. there is also a middle layer copper fill that should mostly shield digital signals running on the bottom layers.

[Kleinstein]

If one has reasonable guard traces from bootin, chances are this can suppress much of the capacitance and losses in the PCB. So chances this would be than good - as is it is already good enough for most uses, especially as the current gets smaller with 10 PLC.  The case with AZmux out lifted has some 6 pA of difference from -10 to +10 V and thus some 3 GTohm of input resistance. The very few cases that need a near electrometer perfomance could use the OPA140 input buffer in non AZ mode and thus some 1-2 pA of bias and 10 Tohm range input resistance.

[julian1]

Driving bootin may be one of the next steps to try.

Agreed. Also, it brings the discrete jfets of the amplifier into play. 
 
I've populated the amplifier in a simple configuration - jfe2140.  5V6 zener.  tle2071 op.

An air-wire connects mux-out to the amplifier input.
The board is *not* well cleaned due to a few bodge wires that limit access.
But this also provides a good test of guard effectiveness.

- with bootin tied to gnd.

leakage 1000nplc/off
  +10V    -0.7mV. -0.8mV -0.8mV. 
  0V      +1.1mV +1.1mV
  -10V     +5.4mV +5.3mV

charge 1nplc
  +10V    -7.6mV. -9.2mV -9.3mV.  -8.9mV
  0V     +6.9mV +7.2V
  -10V    +22mV +23mV.


- identical except bootin driver op added.
(this copies the voltage on the copper fill under the lifted mux-out pin, and surrounding the amp input air-wire connection, as well as other sensitive amplifier pins)

leakage. 1000nplc/off
+10V    +0.7mV. +0.7mV.
0V      2.2mV.  2.1mV
-10V    5.2mV.  5.3mV

charge 1nplc.
+10V    -0.9mV  -1.0mV.
0V      4.9mV  4.8mV. 4.8mV.
-10V    +11.2mV  11.3mV

So it looks like bootin is quite effective at reducing the charge difference at different dc inputs..

[julian1]

I added the dcv ranging (100mV,1V,10V,100V,1000V) components (hv divider etc) and functions.
It work wells with the amplifier in a simplified non-compound configuration.

Also, look to have discovered the issue with the 4053 precharge-switch behavior compared with prior standalone tests.

The current-source (1mA) for the bootstrap zener terminates at the 10R (R405) included as an option to unload the capacitance of the guard fill.
But given this is after the op feedback node, a 10mV offset is created across the resistor.

So the precharge-switch was switching between input and boot but with a small 10mV offset.
This was not clear in simple tests, but easy to see on a scope at the amplifier output with gain=100x (why the hell is there a 1V offset during the pc phase?!!).

Changing R405 from 10R to 0R makes boot=signal.
But after fixing this, the previous good trim for the max4053 is upset (too negative even at low 2.7V supply).

However, charge contribution is more consistent with previous test data.
And the bad leakage from lv4053 has disappeared.

With a 0V/BOOT input offset relative to the -ve supply rail,
- max4053 adds negative charge.
- lv4053  adds positive charge.

The trick of trimming charge by adjusting the supply voltage works for both max4053 or lv4053.
But there is not quite enough adjustment headroom/range, to null the charge offset for a 0V input relative to the negative supply rail.
eg. max4053 is still too negative at 2.7V supply.  and lv4053  is too positive at 5.5V supply.


But it is possible to compensate with a small cap from the precharge signal to the output of the pc switch.
And signal polarity, and switch phase, can be made to cancel the positive charge offset of the lv4053.

anyway, I didn't want to put extra time into this, but it is more clear now what is going on, and perhaps interesting enough to share.

- With sn74lv4053.   at 2.7V.   10p. compensation cap.
- use lower supply voltage for lv4053 to minimize leakage, and rely on cap to trim charge offset.
     
leakage  1000nplc / off
+10V    -0.9mV.  -1.5mV
0V.     -0.5mV   -2.2mV
-10V    0.9mV    1.9mV.

charge 1nplc
+10V    -6.1mV  -5.8mV.
0V.     -2.6mV -2.4mV
-10V    +5.8mV  6.2mV

[Kleinstein]

Getting good leakage with even the cheap SN74LV4053 is nice.  A lower supply is usually no problem, unless one wants super low noise for a more nV meter like version. This would anyway need a few more changes to keep the resistance and thus noise in the path low.

For the charge trim there would be not only the overall supply voltage, but also a possible split in a positive and negative supply relative to the input / guard.
10 pF of capacitance for the compensation of the charge injection looks large, but if it works why not. Much smaller capacitors are a bit tricky anyway.

The leakage current is really low (1 mV drop over 10s with a 10 nF capacitor means 1 pA).  So the 1 PLC case would between +6 and - 6 pA.  That level of leakage is likely a mix from the input MUX, the pre-charge circuit, the 2nd MUX, the amplifier and possible PCB leakage. With the switches this is well below the typical specs and things can vary with units.

A point that may be interesting is how much switching spike is visible at the input  - not so sure how to measure, maybe just the scope input directly ?
The older DMMs (e.g. 3458, 3456, K19x) seem to use relatively slow switching and this one can expect relatively broad pulses. Here the switching is fast and the current pulse starts out short and is than somewhat broadend by the RC filtering.

[julian1]

Added some more functions,  aper, nplc, fixedz, azero off mode, and a non-az. 'electrometer' mode using the boot op.

For observing switching from the input side, I hooked up the input to a 10x probe - so a 10Meg input-impedance.
the mains 50Hz mains is ever-present on my probes.
But what is worse is that the 10p comp-cap (switch-node to output-node) really pushes/smacks around the signal.

It is possible to change to the original scheme with a compensation-cap from switch-node to input-node.
And using lv4053 (unlike max4053) this also works.
Experimentation shows an air-capacitor formed by two wires crossing - shifts the charge-offset about 1mV.
And a 3.5pF trimmer, set to 2.5pF according to an lcr meter shifts about 5mV.
With lv4053 at 2.7V it there is still about 7mV more trim needed to null the offset.
So this could be reasonably achieved via a combination of fixed-cap and/or trimmer.

But with this circuit arrangement too, the cap really pushes the signal around a lot.

Perhaps the most interesting case - is when no cap is fitted.
Here, the switching effects are negligible and very hard to observe.
There is some pertubation that can be seen at the amp output with G=100x.
And this also matches what I see with 34401a input, with the same test setup - it's very hard to see switching artifacts - maybe just a bit of non-linearity impressed onto the mains hum.

What is puzzling, is that I kind of expected to see the 4053 cmos switch also push the signal around through a half-phase transition (the comp-cap is only meant to offset this).
So maybe the cmos charge-injection is just really low, and the below observable limit.

And perhaps the accumulation offset on the 10nF, is some factor other than switching charge-injection.
Perhaps it is due to Vos of the boot op, or asymmetric leakage with voltage spiking.
If this other factor is removed then perhaps no cap is needed.

[julian1]

Huh, it looks like the forum image upload really does reverse the intended image order. 

The other thing I was thinking about, would be a kind of phased coupling approach.
So an independent ctrl node could deliver a transition in one polarity into the output when the precharge-switch is muxing the signal-node.
And then dump the opposite polarity when the precharge-switch is muxinig low-impedance boot.

On another point, perhaps the complexity of introducing a dac in the 3458a is for ratio-metric switching - where hi-side jfets need to be switched as well, and charge-injection compensated.

[Kleinstein]

The spike with the 10 pF cap in place looks quite strong, while the case with no extra cap looks really good - essentially only the 50 Hz hum. To get a better signal one could maybe use direct coax connection to the scope - so no probe and largely shielded.

Are the tests for the input spike done with the 10 nF capacitor connected ? I guess not as this capacitor should stretch the spike much more.

The 10 pF capacitor was shifting the average input bias, which can have many other reasons than charge injection. So I think the logical point is to skip the capacitor. The case with 1 PLC had a drift rate of some 5 mV/10s and thus some 5 pA of input bias, which is totally acceptable. Some 2 pA are also there without switching (e.g. the input mux and OPA140 buffer input). If reelly needed one could consider compensating the input bias in a different way, e.g. offest to the precharge signal (like in the 34401, 3457,...).

The complexity in the charge compensation of the 3458 is because the switching is with JFETs. The CMOS switch chips have quite good chearge compensation build in from using the N and P channel. I don't know if the 3458 uses the DACs with fixed settings (determined during a factory cal run) or if they are adjusted depending on the voltage or maybe signal source (e.g. different for the HV divider or shunts). The 2 DACs could just be a fancy substitute for 2 pots in the 3456.  For the ratiometric measurement I see not charge compensation in the 3458 - this would get the full spikes from the input JFETs. This would also apply to the new front end with the MUX before the precharge part.  To avoid this one would need a precharge circuit for every critical input (e.g. 2 voltage inputs and the HV divider) and could drop the MUX before the precharge part. This is how I have it planed and with the LV4053 this also looks sensible. 

[dietert1]

The image with the amplifier output is nice. I think one can see the two precharge phases. Though it's somewhat surprising that both of the precharge phases show the input signal on the amplifier output.
Then there are two spikes of opposite sign when leaving the autozero phase, the first one very short, the second one more like the input side spikes of the compensation cap tests. As far as i understand charge injection depends on those asymmetries
- Autozero phase on and off
- Precharge phase on and off during autozero phase off.
One would need a little more effort the generate a "perfect" compensation signal.

Regards, Dieter

[Kleinstein]

The 2nd "pre-charge" phase for the step from the input signal to the zero reading is not really a precharge of the amplifier, but more an isolation of the MUX switching. The ground path does not really need a pre-charge. Naturally the off switching of the MUX is much less intrusive than the on step. So this part is naturally less intrusive. There still seems to be a little offset / shift.

There us a chance the at tiny bit of wire capacitance (e.g. 0.1 pF range) may be about right to compensate the small visible spike when switching from the precharge to the actual input signal.
This spike would be the part to compensate with a capacitance, not the net contribution to the bias.

For the charge injection we have to distinguish between the net charge effect for a switching cycle, like here with the DMM input and the charge injection in the switch specs - that is usually only the switch off part, like relevant for the S&H stage. Besides capacitance to the control signal also the capacitance to ground (or the switch supply) can effect this charge injection.
The net contribution to the bias depends on the symmetry between the peaks for switching on and off.
The charge injection on switching a CMOS switch off depends on the symmetry in the impedances.

[julian1]

The waveform pics are all use the ordinary dcv ranges. 
The accumulation cap (C410) reserved for timed tests is not engaged.
At 2.7V, the measured in-circuit rds-on is still really low - 25R for lv4053. and 170R. for max4053.

i agree the size of the cap needed to compensate the '4053, based on waveform pics, makes it mostly infeasible.
charge-injection is already well compensated due to nmos/pmos design, and by the bootstrap that keeps input constant wrt the supply rails.

But there is still an apparent leakage/bias that shifts the offset seen in the 10nF accumulation cap tests.
And this has some dependency with switch frequency.
So it is not possible to compensate with say a fixed 100G resistor to the bootstrap rail.

The other way to manipulate this is by changing the boot v input offset slightly.
So similar, to the original mechanism, to trim nmos/cmos contribution using the dedicated extra op-amp.

But there may be a simpler way - by intentionally creating an offset on R405.
ie. to trim in the range of the Vos of the opa140, R405 could be a 0805 0.1R current-sense resistor.
So with 1mA source, V=IR, -> 100uV.

And the opposite polarity (if needed) could be done with a negative current-source terminating at the boot node.
For a negative current-source,  adjustment could be made -0.1 to -2mA, via the negative-source emitter leg resistor (even a trimpot), to allow trim on R405 ~=  +-1mA.

We just need to make sure other parameters are not disturbed - particularly constant leakage, which seems to be an issue for lv4053.


I also need to check that the FP5V supply is not dropping when the 4053 is switching fast, since we know the charge-offset has a dependency to the supply rail.
The buffer npn Q411 was removed, in order to get the 2.7V with the zeners I had on hand.

[Kleinstein]

The input current is already pretty low (e.g. 5-10 pA range) even with 1 PLC AZ cycle. If really needed one could use a little longer integration at a piece. I see no real need to compensate for it. This is within the specs for the high end meters (e.g. HP3458, DA1281, Fluke8858).  The input current with 1 PLC is pretty much on par with the curve for the 3458 in this post:
https://www.eevblog.com/forum/metrology/analog-frontends-for-dmms-approaching-8-5-digits-discussions/msg5087488/#msg5087488
Chances are the data were for 10 PLC as the default speed.

If one really wants to compensate such a tiny current, one could consider a little light to a low leakage diode and there are a few glass case types. It does not take much for a few pA.
Light can also effect the bias on some chips in a plastic case, especially the thinner ones.

To generate an offset for the pre-charge voltage one could use less current a a bit larger resistor. It is gneral a good idea to keep the power low to reduce thermal effects. Thermal fluctuations in combination with thermal EMF or similar can be limiting the LF noise.

[julian1]

To show the data for lv4053 again, with compensation caps removed.
I agree, the 10nplc case is good. 2.7mV to 6.7mV.   So. 2.7pA to 6.7pA input bias current, across the +-10V input range.
Ideally, the offset of 13mV for 1nplc at 0V dc-bias could also be nulled.
But not if it adds a lot of complexity.


input dc-bias
10V
  1000nplc/off    1.8mV. 0.6mV.   0.1mV.  1.4mV.   varation recorded depends on switch phase.
  10nplc          2.7mV. 2.7mV    2.7mV.
  1nplc           10mV   10.2mV.
  0.5nplc         18mV   18.9mV.

0V.
  1000nplc/off    0.7mV. 0.7mV,   1.9mV
  10nplc          2.7mV  2.6mV
  1nplc           12.6mV 13.8mV.
  0.5nplc         24mV   24mV

-10V.
  1000nplc/off    2.0mV  2.8mV 2.0mV
  10nplc          6.7mV  6.7mV
  1nplc           20mV   20mV. 20.5mV
  0.5nplc         32mV   34.2mV


Edit. A small resistor at R405 looks like it should work and can create a constant offset shift at all input biases. But a negative source is needed for lv4053 (existing positive source is ok max4053).  But I probably won't tinker more just at the moment.

[David Hess]

If one really wants to compensate such a tiny current, one could consider a little light to a low leakage diode and there are a few glass case types. It does not take much for a few pA.
Light can also effect the bias on some chips in a plastic case, especially the thinner ones.

Before I knew enough, I designed one circuit which had to use hermetic packages and found that the glass diodes were most sensitive to near infrared causing excessive leakage.  For some reason instead of black paint, we dissolved black mastic in thinner and used that as paint.

If I did that design now, I would use transistors as low leakage diodes and bootstrap them to easily achieve less than a picoamp.

[schmitt trigger]

Subscribing to thread

[Alex Nikitin]

If I did that design now, I would use transistors as low leakage diodes and bootstrap them to easily achieve less than a picoamp.

No, BAV199 diodes from Infineon or NXP would be much better (and not light sensitive). Here some leakage data on several BAV199 makes at 26C, both for reverse (0-100V) and forward (50mV-500mV) bias, vertical scale in Amps, horizontal in Volts. Measured with Keithley 617.

Cheers

Alex

P.S. - added a comparision between some of the worst of BAV199 (from Diodes and Multicom, IIRC) and 1N4148, just to put this matter into perspective

[DeltaSigmaD]

@ Alex: Thanks for these measurements. One point must be considered with the BAV199: this diode has a long reverse recovery time, too slow for some applications. I assume that the BA199 has a wide depletion zone without deep traps dedicated to work as fast recombination centers, as the case with the 1N4148. Therefore, the leakage current and the capacitance are very low, but minority carriers have a long life time.

[Alex Nikitin]

@ Alex: Thanks for these measurements. One point must be considered with the BAV199: this diode has a long reverse recovery time, too slow for some applications.

Nothing is perfect  . It is worth remembering however that at the current levels discussed (picoamps and below), a microsecond is not much, as 1pA is about 6 electrons per microsecond.

Cheers

Alex

[David Hess]

If I did that design now, I would use transistors as low leakage diodes and bootstrap them to easily achieve less than a picoamp.

No, BAV199 diodes from Infineon or NXP would be much better (and not light sensitive). Here some leakage data on several BAV199 makes at 26C, both for reverse (0-100V) and forward (50mV-500mV) bias, vertical scale in Amps, horizontal in Volts. Measured with Keithley 617.

The BAV199 is only *tested* to 5 nanoamps, which is not practically any better than a small signal bipolar transistor, so either must be graded or selected anyway.

The BAV199 has a huge advantage in reverse breakdown voltage, comparable to a base-collector junction if you what to go that route instead (1), but if bootstrapping is used, then the base-emitter breakdown voltage is sufficient, and the base-emitter junction is lower capacitance and orders of magnitude faster (2) than a BAV199.  The 60 millivolt conductance that you measured is identical to a 2N3904 base-emitter junction, so that is a pretty good diode, but no better than a transistor.

5 to 15 volt low leakage fast diodes used to be available, but even in the past, they were expensive simply because there was so little demand for them.

(1) A base-collector junction has higher capacitance and is slow, but the BAV199 only bests it with better conductance.

(2) I measured 600 picoseconds on typical 2N3904s, which is consistent with fast low voltage low leakage diodes of the past, but I would like to repeat this measurement with better equipment.

[Alex Nikitin]

I am not in a business of selling diodes, I only share my data. There are diodes with better leakage specs, for example FJH1100 with the max leakage current of 3pA at 5V and 10pA at 15V, with the price over $10 each, much lower max voltage and comparable capacitance and current ratings. I did include this diode in the graphs by the way - have a look *. And obviously, I've measured many diodes from each of different makes and batches, the performance curves as on the graphs are pretty typical and I haven't seen any real outliers. For the price difference you might just as well measure each and every diode before using it  .

Cheers

Alex

* - P.S. and the FJH1100 is light sensitive even if the black coating is not damaged

[Kleinstein]

Diode leakage is not really an issue in the front end so far. The clamping diodes can be bootstrapped and thus only see a low voltage in the 1-5 mV range. One version has a AC optocoupler input (IR diode) to do the clamping. These have a relatively high forward voltage and thus likely also low leakage.

For the lowest leakage one may have to gamble on using the typical specs. The limiting specs are often just limitations on the test setup and actually performance is often way better and most of the parts are likely close to (or even better than) typical.  The question is if it is worth testing the parts upfront, or just use in the circuit and than check the complete or maybe partial populated PCB. Even if parts test good before, soldering may change things.

The critical leakage is more from CMOS switches or alternatively JFETs used for switching.  Modern CMOS switches like the ADG1208 seem to be pretty good - as measured here even better than typical specs.
The CMOS switches are much easier to use than JFETs. Still JFETs are nice in that they are essentially no power and essentially no leakage when on.  Ideally not that many swiches are really critical with leakage.

A point I see is that it helps to design for low power. Some heating (5 to 10 K) above ambient has a positive effect on humidity and thus surface leakage, but more is bad with thermal fluctuations and semiconductor leakage.

[David Hess]

Diode leakage is not really an issue in the front end so far. The clamping diodes can be bootstrapped and thus only see a low voltage in the 1-5 mV range. One version has a AC optocoupler input (IR diode) to do the clamping. These have a relatively high forward voltage and thus likely also low leakage.

The wrong diodes will still leak at millivolt levels, so there is still cause to use low leakage diodes.

Using an optocoupler input diode is clever.  LEDs when painted also make useful low leakage diodes and also achieve low leakage at low forward voltages.

[julian1]

For the adc, the design is similar to the one in the diy-voltmeter thread.
A difference is the integrator reset which is managed with another spdt 4053 mux, instead of being muxed through the main buffer/amplifier.

configuration -
ref lt1021/7V.
amplifier lsk389. will revert to jfe2140 as baseline, when get some more.
bench supply.
a biscuit tin lid covering the pcb helps to reduce noise.

The main column of interest is the last one,
10nplc noise is around 0.33uV RMS.  1nplc noise around 1.4uV RMS. I believe this is mostly from the adc input resistors.
reference noise in the adc, should most cancel, for a lo measurement/sample.

- sample ref-lo with no amplifier gain,

az 10nplc
> reset; azero on; nplc 10; himux ref-lo ; azmux ref-lo ; gain 1; buffer 30;  trig
counts  10002 2022507 1977610    891 4000001 (lo)  (hi -0.000,003,7V) (lo 0.000,003,8V, 0.000,003,7V) az meas -0.000,007,5V   mean(30) -0.0000077V, stddev(30) 0.31uV,
counts  10002 2022490 1977610    232 4000001 (hi)  (hi -0.000,004,6V) (lo 0.000,003,8V, 0.000,003,7V) az meas -0.000,008,3V   mean(30) -0.0000077V, stddev(30) 0.32uV,
counts  10002 2022507 1977610    891 4000001 (lo)  (hi -0.000,004,6V) (lo 0.000,003,8V, 0.000,003,8V) az meas -0.000,008,4V   mean(30) -0.0000078V, stddev(30) 0.33uV,
counts  10002 2022490 1977610    229 4000001 (hi)  (hi -0.000,004,3V) (lo 0.000,003,8V, 0.000,003,8V) az meas -0.000,008,1V   mean(30) -0.0000078V, stddev(30) 0.33uV,
counts  10002 2022507 1977610    889 4000001 (lo)  (hi -0.000,004,3V) (lo 0.000,004,0V, 0.000,003,8V) az meas -0.000,008,2V   mean(30) -0.0000078V, stddev(30) 0.33uV,

az 1nplc.
>  reset; azero on; nplc 1; himux ref-lo ; azmux ref-lo ; gain 1; buffer 30;  trig
counts  10002 202317 197812    726 400001 (hi)  (hi -0.000,009,9V) (lo -0.000,001,1V, 0.000,001,8V) az meas -0.000,010,2V   mean(30) -0.0000071V, stddev(30) 1.28uV,
counts  10002 202317 197812    713 400001 (lo)  (hi -0.000,009,9V) (lo 0.000,002,7V, -0.000,001,1V) az meas -0.000,010,7V   mean(30) -0.0000072V, stddev(30) 1.41uV,
counts  10002 202317 197812    723 400001 (hi)  (hi -0.000,007,0V) (lo 0.000,002,7V, -0.000,001,1V) az meas -0.000,007,8V   mean(30) -0.0000072V, stddev(30) 1.39uV,
counts  10002 202317 197812    716 400001 (lo)  (hi -0.000,007,0V) (lo -0.000,000,2V, 0.000,002,7V) az meas -0.000,008,3V   mean(30) -0.0000071V, stddev(30) 1.37uV,
counts  10002 202317 197812    721 400001 (hi)  (hi -0.000,005,0V) (lo -0.000,000,2V, 0.000,002,7V) az meas -0.000,006,3V   mean(30) -0.0000071V, stddev(30) 1.38uV,


There is a -8uV difference when ref-lo is sampled from the himux versus the azmux - in az mode, regardless of nplc.
The ref-lo trace is kelvin sensed at the gnd pin of the lt1021.
The only adc count that changes (for 1nplc example) is the rundown count, so it is not a calculation artifact.

The difference is a bit large to be a thermocouple effect on ic pins/ or copper trace.
So I don't like this.
maybe switch charge-injection when the az mux switches between the lo/boot from the pc-switch to the ref-lo.
and/or distribution for different impedances of the mux paths?
But I still wouldn't expect this given that ref-lo is a low impedance input.
EDIT. Also if it was a charge effect on would expect to see the effect change at different nplc/apertures.

The other LO that is common to himux/himux2 and azmux is the star-lo.
So I should check to see if that shows the same issue.
Also there is the resistor R417 that can match/compensate the rds-on of the hi muxes.


for 10nplc no-az input noise is about the same as the az case.

> reset; azero off; nplc 10; himux ref-lo; azmux pcout ; pc signal ;  gain 1;  buffer 30; trig
counts  10002 2022490 1977610    228 4000001 no-az meas -0.000,004,2V   mean(30) -0.0000038V, stddev(30) 0.34uV,
counts  10002 2022490 1977610    225 4000001 no-az meas -0.000,003,9V   mean(30) -0.0000038V, stddev(30) 0.33uV,
counts  10002 2022490 1977610    232 4000001 no-az meas -0.000,004,6V   mean(30) -0.0000038V, stddev(30) 0.35uV,
counts  10002 2022490 1977610    230 4000001 no-az meas -0.000,004,4V   mean(30) -0.0000038V, stddev(30) 0.37uV,

There is a 3.8uV difference in non-az mode.
But this expected thermal variation (ref, op-amp Vos,resistors) from the calibration baseline point taken about 10-15mins earlier.

[julian1]

For the amplifier, the ref-lo can be sampled with gain,

az, 1nplc, gain = 100.
>  reset; azero on; nplc 1; himux ref-lo ; azmux ref-lo ; gain 100; buffer 30;  trig
counts  10002 204765 195449    840 400001 (lo)  (hi 0.207,785,5V) (lo 0.207,950,7V, 0.207,939,0V) az meas -0.000,159,4V   mean(30) -0.0001477V, stddev(30) 7.82uV,
counts  10002 204748 195449    246 400001 (hi)  (hi 0.207,803,0V) (lo 0.207,950,7V, 0.207,939,0V) az meas -0.000,141,8V   mean(30) -0.0001472V, stddev(30) 7.71uV,
counts  10002 204765 195449    830 400001 (lo)  (hi 0.207,803,0V) (lo 0.207,960,5V, 0.207,950,7V) az meas -0.000,152,6V   mean(30) -0.0001470V, stddev(30) 7.51uV,
counts  10002 204748 195449    258 400001 (hi)  (hi 0.207,791,3V) (lo 0.207,960,5V, 0.207,950,7V) az meas -0.000,164,3V   mean(30) -0.0001478V, stddev(30) 8.06uV,
counts  10002 204765 195449    839 400001 (lo)  (hi 0.207,791,3V) (lo 0.207,951,7V, 0.207,960,5V) az meas -0.000,164,8V   mean(30) -0.0001484V, stddev(30) 8.62uV,

note. amplifier Vos around 2mV.

no-az,  at 1nplc  gain = 100.
> reset; azero off; nplc 1; himux ref-lo; azmux pcout ; pc signal ;  gain 100;   trig
counts  10002 204748 195449    210 400001 no-az meas 0.207,838,1V   mean(30) 0.2078348V, stddev(30) 6.20uV,
counts  10002 204748 195449    211 400001 no-az meas 0.207,837,2V   mean(30) 0.2078352V, stddev(30) 6.00uV,
counts  10002 204748 195449    223 400001 no-az meas 0.207,825,5V   mean(30) 0.2078349V, stddev(30) 6.26uV,
counts  10002 204748 195449    216 400001 no-az meas 0.207,832,3V   mean(30) 0.2078343V, stddev(30) 5.66uV,
counts  10002 204765 195449    946 400001 no-az meas 0.207,847,3V   mean(30) 0.2078348V, stddev(30) 6.12uV,


For the 1nplc, gain=100x case, the az and no-az look similar for noise.
I am not sure how to interpret that.
Is the noise from the amplifier or 99k/1k feedback resistors, or the (amplified) white-noise of the resistance of the muxes/passives before the amplifier?
I kind of expected the az subtraction to cut-out flicker noise in a more observable way.
Or maybe it is evident, given that AZ mode only uses half the HI samples, but achieves similar variation.