Analog frontends for DMMs approaching 8.5 digits - Discussions

[Kleinstein]

The AZ mode reduces the effect of flicker noise by limiting the lower frequency end. If there is not much flicker (the LSK389 are pretty low noise) this effect may not be that large and 30 samples are not that long (less than 1 second in 1 PLC non AZ mode). The non AZ mode noise is not much lower, despite of having effectively half the BW. So there is some low frequency noise, but not very much.

The noise with gain is still not that low as one may hope for.
The 1 PLC AZ mode has a noise BW of 2x25 Hz
The 8 µV are already well more than the ADC noise alone, so most of the noise is from the amplifier, not much from the ADC.
some 8 µV at the output or 80 nV corresponds to some 11.5 nV/Sqrt(Hz) for the input noise.  This is not really good, but also not super bad.

The 11.5 nV/SQRT(Hz) correspond to the noise of about a 8 K resistor. So the 1 K in the feedback can not be the main source. There are likely a few more resistors in the input path for filtering or protection that could add up and the ground sense path may also have resistance, if only for compensation / symmetry.
Another part of the noise may still be from thermal fluctuations. 80 nV are not much and in my circuit I had some 30 nV_RMS from thermal fluctuations.
It may help to look at the frequency spectrum or allan deviation of the noise - to record some 10000 points and plot it. Thermal noise is more flicker / random walk like. Resistor noise is usually white noise and interference / beat frequency to mains may have a distict frequency.
If there is significant popcorn noise (well possible for a JFET amplifier), one can often see this in the time domain, preferrably in the non AZ mode.

The ADC noise shows more noise than expected from the input resistors. With 50 K this would be more like 290 nV RMS noise for the 1 PLC AZ case. The noise is OK at least for the start (maybe close to the KS34465), but still not great.  The ratio of noise in the 1 PLC and 10 PLC mode is around 4.2. This is more than square root of 10 as expected for simply the lower bandwidth. This points to some noise from the run-down part / comparator or possibly quantization still relevant in the 1 PLC case.  I don't have the details to have a good guess on the noise sources, but it is likely more than just the input resistors.

Even with 0 input voltage there can also be reference noise (from higher frequencies around the modulation frequency in the ADC) to contribute to the ADC noise. The +- ref modulation acts like a mixer and bring that higher frequency down to the near DC range.
It is often overlooked, but is relatively easy to fitler out, somtimes even as a side effect of a slow amplifer. Worst case (no filtering effect) it could make up some 1.1 µV for the 1 PLC case.   

8 µV of difference for different ground sensing paths is a bit high for just thermal EMF, but not impossible. Some ICs and also resistors can have relatively high thermal EMF. I have measured some 4 µV as the difference between 2 units of the protection part. Thermal EMF would also be sensitive to warm up and air flow.

[julian1]

To follow up on the 8uV observed difference for ref-lo depending on sense point (at himux or azmux point).
It looks like there really is a small voltage difference there.
The way to confirm this, and rule out AZ/switching issues, is to use non-az mode and collect samples for both cases.
Perhaps the separate/ copper islands used for guards create more localized thermal isolation/differences across the pcb.
Something for the future might be to test dg508 as well.

For noise investigations, a good first-step is probably to swap the lt1021/7V to rule out issues.
For ltz1000, the pcb has a 'normal' pin-out soic-8 dual op-amp.
I have bjt single-supply mc33172 (lacks some LF characterization), and opa2145 (jfet). BB opa2234 look good but are obsolete.

Maybe mc33172 could be used, and then some in-circuit checks done?

If ref-hi was fed to a 10-30uF PP film capacitor (same as a lna), the output could be amplified 100x and then digitized/sampled,
The 10Meg divider/ fixedz, could also set the input source impedance.
I think this should permit measuring ref-noise, independent of its contribution to the adc,
(the assumption is that ref-noise is higher than amplifier noise, which seems reasonable).

[julian1]

op-amp choice for reference.

lt1006 / lt1013. (can't use because of pinout)
  input noise voltage,   0.55uV. 0.1-10Hz.
  input noise voltage   22nV / rtHz. f=1kHz.  23nV/rtHz at 100Hz.
  input bias current    10nA. typ.
  input noise current,  0.08pA/√Hz   f=10Hz


MC33172
  input noise voltage,  Vpp 0.1-10Hz. not given.
  input noise voltage 32 nV/ √ Hz    f=1kHz.
  input bias current 20nA. typ.
  input noise current. 0.2−pA/ √ Hz    f=1kHz.
 
    V=IR,  with 50k input impedance. assuming 'In' has any meaning at 0.1Hz.
    = 0.2e-12 * (1 / Math.sqrt( 0.1)) * 50e3
    = 3.16e-8
    = 31nV.    at 0.1Hz. ?
 

opa2145.
   input noise voltage,   0.32uV. 0.1-10Hz.
   input voltage noise .  7nV / rtHz. at 1kHz.  7.1nV at 100Hz.

[Kleinstein]

Not sure if it is already time to use an LTZ1000 reference. At near zero input the reference noise to possibly worry about is the higher frequency (e.g. 10 kHz to some 100 kHz) and this is relatively easy to filter out with a relatively simple RC (e.g. 1 K and 1 µF).

Even if using the LTZ reference it would be good to also have some filtering there.

The reference noise is also only one possibly source of extra noise.
I would exclude extra 1/f noise, like excess noise of resistors as the 10 PLC case is even lower noise density.
Looking at the noise data as a plot could help - maybe something really low frequency (e.g. supply drift, a beat frequency with mains, thermal). Also a schematics of the ADC part would help and make it less guess work.


AFAIR the transistor part at the LTZ1000 has a gain of some 200 and this should be enough to attenuate the OP-amp noise and drift by about that factor.
In theory the MC33172 should be just OK, though a slightly odd choice. The current noise and maybe drift of the input bias could be an issue.
The OPA2145 should be OK too - much better specs in most aspects, just a bit unclear about long term offset drift. I would consider it more like overkill.
The higher BW may want some care.

The OPA2234 is kind of a predecessor to the OPA1642 and a bit on the fast side and high in power consumption.

[julian1]

Is there a go-to octave/matlab script for spectral decomposition/ allan variation for a larger sample set?,
I've done fft on time-series data a long time ago.

To potentially rule out some basic issues - I swapped the ref over, changed the rundown bias resistor (R902) from inexpensive thin-film to zfoil to exclude thermal effects.
Also added gain to the slope amplifier,  from opa140, 10k/10k to opa140 2.15k/21.5k (2k loading on integrator output is probably too high).
In the past I tried perturbing the slope-amp with bjt op-amps - ne5534, op27, op37, lt1358. but without seeing much affect.
the reset resistor (R903) is 3.74k. not 20k. as indicated on the schematic (also a load on the integrator op).
only the lt5400 resistors are populated. the discrete resistors are to experiment.

The biggest difference is seen by adding tin lid for shielding. 0.6uV -> 0.4uV.  10nplc. az off.

Two things in my mind are  - to populate the RC (C916,R909) between the adc current and integrator input.
I remember probing it, and it is certainly spikey. but I never got around to adding RC here.
I should also try sampling boot on input, to by pass the 2k+2k+mux rds(on). input source resistance (R425, R431).

But maybe potentially distinguishing white-noise/ flicker noise, would be easier with a frequency/noise plot.

[iMo]

I've been just using the TimeLab for ADEV/MADEV while looking at an ADuC ADC here..
It makes the analysis "online" as the data stream off my ADC (via bluetooth into Teraterm, TT logs into a file and TimeLab reads the data off the file in the real time, setting Aquire->Aquire from the live ASCII file). Example below..

[Kleinstein]

The reset resistor does not matter directly for the noise, a larger resistor only makes the reset slower and thus more time needed for the reset. 4 K and 2 nF are 8 µs time constant and thus likely some 20-40 µs as a suitable time. The 3.74 K sound about reasonable as they also load the integrator.

The RC element C916 and R909 is defintely a good idea. Even if not fine tuned it generally helps with the settling of the integrator. That is less ringing visible at the output of U906. That output is anyway a good testpoint to check the integrator settling and how long one should wait between switching events. The values for R910 and R911 also effect the settling. They are not an alternative to adjusting the integration capacitor, more a thing to trim the speed of U906, e.g. to allow different speed combinations.

The slope amplifier has also the task of limiting the bandwidth for the signal to the comparator. More BW here also means more noise. Less BW (e.g. more gain at the slope amplifier) gives a slower reaction and more overshoot and thus a slightly slower rundown for the slow slope part. A rather high BW with a relatively large integration capacitor could be an issue and add residual charge noise, so noise that gets higher for short integration. Part of the noise seen is of this type (about 4 :1 ratio instead of square root 10).

Another possible issue would be that there is only partial filtering at the references. When I removed the filter capacitor in my ADC with a LM399 reference, the noise for 1 PLC went up from some 550 nV to some 1.3 µV.
A more minor issue is that the resistors at the reference amplifer are relatively high. It looks like 8 x 10 K in series for the whole amplifier and thus 40K+40K seen by the inverter part. This effectively adds the noise of a 20 K resistor. Still this is only a more minor noise source. So skipping RN902 and double R902 may be a thing for later.

In the plan the flipflops to syncronise the control signals are 74HC175. These have quite some jitter and the LV or AC series would be better. Depending on the clock signal also ACT or similar to work with a smaller input signal.

For the integrator input it looks like the plan is for 40 K at the reference and 50 K for the input - just like the HP3458. This would give an about 14 V FS range, but may result in more gain drift from the switch resistance. I would expect an extra   -1 ppm/K from this. So not very much, but avoidable. It also increases the resistor noise a little over the case with 3 x 50 K or 3 x 40 K. Using a +-14 V ref instead of +-12 V as in the 3458 is the better alternative to the lower resistors for the references.

[julian1]

Thanks Imo! I tried a batch file import around 11k obs/ 4 minutes, copying your config - with decimal frequency for data field, and 0.02 sample rate.
The axis don't pick up labels or units. Perhaps they need to be set up by hand?, or it's a wine issue?

[julian1]

Allan plot using NXP octave code from, https://www.nxp.com/docs/en/application-note/AN5087.pdf

1nplc, no az.

Edit. fix freq.

[Kleinstein]

The Allan deviation showns the normal square root slope below some 1 s as expected for mainly white noise. This points to a relatively low level of 1/f noise - so not much excess noise from resistors.  The bump at some 10-20 s is a bit strange. It could be some typical frequency of popcorn type noise in the OPA140 or front end amplifier. Another thing could be a thermal effect. I have seem a comparable frequency as thermal oscillation and in non AZ mode there can be some sensitive parts at the integrator.

The raw data look like there is some rounding / quantization noise included. Overall it is pretty low drift for a non AZ mode of operation.

[iMo]

@julian1 - your data in my TimeLab (win10)..

PS: added the same with the latest TimeLab 1.71a beta

[julian1]

I've made some changes to improve adc noise a bit.

changes creating obvious improvement -
  - swap lt5400 to morn resistors that I had at hand. these look superior from Castorp's published research, reduced 1.3uV  to 1uV RMS 1nplc.

  - nov 18. lowering freq. 330p/84kHz to 1.5n/ 19Khz. reduced 1uV to about 0.7uV RMS 1nplc.
    This improvement is less than the expected ( Math.sqrt( 84kHz ) / Math.sqrt( 19kHz) = 2.1x ), if integrator op-amp noise was dominant.


other changes, with less noticeable influence

  - swap synchronizer 74hc175 to lv175, not sure how I overlooked this.
  - swap comparator from lt1016 to tl3016, mostly to reduce current and heat. lt1016, is horrible and the to-92 L7805/7905 regulators are hot and can barely be touched.
  - shallower rundown, less quantitization, although past tests suggest this may affect INL a little due to DA.

  - also increased slope-amp gain (to reduce slope-amp BW - and gave more hysteresis for the comparator, to ensure no output glitching/meta-stablility issues.
      (control over the comparator latch to prevent glitching, is not effective if the control cannot first sample a clean value on the clock edge).
      this seems to be more an issue for tl3016 v lt1016.
      although none of these changes appeared to influence measurement noise.

  - I couldn't see any difference, from adding LP filtering of the ref for HF noise with LC 1k/1u PP or x7r,
      Perhaps a series RC bypass to ground would be better - similar to the 1u/5R of the adr1399 reference circuit?
      - the ref sits right next to the adc current source ladder which is good.
      but the ref-lo and ref-hi traces cross the adc circuitry to reach the input muxes, so this could be an issue.
      It's not possible to LC filter the references here, so this has to be addressed with an improved layout.

  - using 34401a transformer to power the board, instead of a bench supply.

- I believe it's possible to see the adc noise on a scope.
    Hooking up scope/digital probes does ground reference the circuit, and introduces additional EMI, which increases measurement stddev 2x to 3x.
    But it is still possible to visually correlate the waveform variance and magnitude, which is mostly associated with runup (horizontal displacements of the waveform at the end of runup),
    rather than anything around rundown/comparator sampling.

- it should be possible to do a kind of rundown re-sample/multi-sample. So after final rundown, the output could be steered to perform a second rundown cycle
    And ths would improve rundown sampling noise.
    But given what can be seen on the scope, I doubt that it will help.
    Also switching to an ADC to multi-sample the rundown output would be more effective and simpler.

[Kleinstein]

There are quite a lot of possible relevant noise sources for the ADC.  And some of the details of the ADC decide which a really relevant and which are hardly noticable. The more important ones are:
1) The resistors at the integrator :  with equal resistors this behaves like 2 of the resistors in series to the input.
2)  low frequency noise of the integrator. This is usually 1 OP-amp with a noise gain of about 2 (with equal resistors at the integrator) or a bit higher with smaller resistors for the references.
     With a BJT also the current noise can matter, it is effective with the input resistor to the integrator and some DS are a bit optimistic.
3) Jitter from the clock, flip-flops and switches. This is more inportant with faster modulation and slower chips.
4) Capacitance of the ref. switch input side leading the "reset noise": may be an issue with fast modulation and relatively large capacitance. Should be OK with the LV4053 switches.
   Fluctuations in the charge injection acts similar.
5) low frequency noise of the reference amplification (usually 1 OP and the resistors at the inverter)  - should be a more smaller part
6) higher frequency reference noise, that is modulated by the runup patters and gets mixed down. Often one has some fitlering for this, by caps to stabilize the reference amplifiers.
    This may be an issue in some of the Keithley meters as they tend to use fast amplfiers in the ref amplification.
7) higher frequency noise of the integrator and slope amplifier leading to noise at the comparator. This noise is usually effective with the BW of the slope amplifier. The size of the integration cap also enters here. This noise is part of the residual charge noise and this more relevant for short integration.
Quatization noise, usually for the residual charge and thus more a thing with short integration. This part can usually be calculated quite well.
9) switching between different run-up patterns that should ideally give the same result, but with a relatively high DNL error would also give noise. This is more an issue with an auxiliry ADC for the residual charge, less with a reset.

The LT5400 resistors should be OK and low noise it may be the resistor value that can make a difference.  Noisy ones are more like AORN and NOMCA and some separate thin film resistors (e.g. ptf56 series).


Changing the modulation frequency from 84 to 19 kHz and the corrosponding change in the capacitor is expeced to reduce the effect of jitter, but get the resitual charge part more important.

P.s. getting to 0.7 µV RMS for 1 PLC is already quite good.  Expect a mix of noise sources if one is that good.

[julian1]

It is probably good to test other circuts for basic function, to be in a position to make revisions.
This is an attempt at an ohms current-source - very classical, with one resistor per range.

overview,
- tested. appears to work, can iterate fixed current-ranges (1uA-10mA), without oscillation, although I havent tried with the protection.
- kept simple, in the sense that different switch paths are all identifiable and separate. although it's open to the criticism too many switches and resistors are used, creating a poor BOM.
- agn200 relays are nice and compact. about the same footprint as an soic part.
- TC stability should mostly be determined by resistor choice - a custom footprint allows 0805 to 2010 parts.

design,
- there are two independent output sections - a high-current (dmos pfet), and low-leakage output (pjfet, depletion mode fet). relay K601 selects the output stage choice.
    this requires an extra switch, but is more open/flexible than than trying to combine a low-leakage and high-current output in the same circuit (34401a,3458a).

- for the 10mA range, relay K602B is used instead of a U605 mux channel, to avoid excessive voltage-drop through the mux.
  The original schematic has an option for a low resistance mux u608 (eg. adg1408 rds-on=4.7R) for the 10mA and 100mA ranges, but I decided against the 100mA, and it has been removed. 

- K602A (with K602B) was added to support a relay state combination for galvanic off isolation.
    but may also help protect the low-current output-section from accidental engagement of high-current (10mA) drive.
    not sure if useful, and it is currently shorted with a jumper.

- Q615 is used to (digitally) sense negative over-voltage conditions, and is taken straight from Kleinstein's design.


what i don't like,
- I feel relay k603 that selects the bottom divider resistor should be able to replaced with a mux.
    But I cannot see how, without adding the TC sensitive mux-resistance to the divider, or else by duplicating other circuit elements.

- the zener (replacing d601,d603) setting up the working headroom, could be made user-switchable for a lower output compliance voltage.
    But would require another mux...

[Kleinstein]

The leakage of the P-FET in the current regulator should not matter. If at all it is about the gate leakage and even the larger P fet should be good enough here. The actual leakage is usually vial the protection and performance can vary. So I don't think the switching of the p-fets for high / low current is really needed.

The part that may want switching would be the OP-amp to do the regulation, as this is a compromise between bias dirft and noise / voltage drift. The higher currents would be happy with something like an OPA387 for the regulating OP-amp for low voltage drift. The lowerst currents (e.g. 1 µA and less) would prefer the OPA140/OPA145, as here the bias current and current noise is more relevant. For the bias it is actually only the current drift that really matters. The normal bias is just a part of the test current. Only the current ratio between the 3 V and 0.3 V ref voltage would differ a bit.
So if one wants to switch between high and low current parts it would make sense to switch more, e.g. the complete current source up to the protection.
Using a dual OP-amp for U603A/B is not such a good idea as the needs are a bit different, with the smaller currents. U603A wants low drift, but the bias is not that critical as long as it's less than the test current.

Another point for the higher current ranges is that the power loss on the current setting resistors gets quite large. So 10 mA test current would be more set with 1 V and 100 Ohm and not 3 V and 300 Ohm. Even a 2010 foot-print may be a bit on the small side for the 10 mA test current - I have 3 pieces of 0805 in parallel and thermal effects are still quite large.

With a 10 mA test current one may want to have a way to turn of the current in case there is a significant foreign negative voltage. The SOA if the small SOT23 transistor is usually not that good. One may get away with a software solution, though not ideal.

The diodes in series with the MUX chip mainly make sense when there is an additional resistor to an auxiliary voltage level to catch MUX leakage. This way the drive side MUX gets non critical (e.g. could use something like TMUX4051 or HC4051 with level shifters). This way the leakage is from the diodes instead of the MUX chip. With the rather good ADG1208 one may get away with just the MUX, and skip the diodes.

For the K603 part the simple way would be to work with a fixed current source from the low side and switch the resistor tap at what is now R608.
Not sure if one really needs a buffer for ref. low, of simple GND may be good enough. A buffer would anyway need a negative supply, as it would need to drive current at essentially GND level.
Switching to a lower output compliance voltage could be rather crude with transistor switching - this is not about precision, but only order of magnitude. There is anyway some drop at the protection.

For stability with an inductive DUT one may want a resistor (e.g Kohm range, but depends on rest of circuit) in parallel to L601.

[julian1]

The actual leakage is usually vial the protection and performance can vary. So I don't think the switching of the p-fets for high / low current is really needed.

For the split output section, I probably need to actually measure/test the gate leakage of pmos / bss84, and decide on parts to determine if it is justified.
The adg1208 mux and jfet input of U603A have leakage in low pA.
So anything in that range would be fine for low-current ranges.
3458a uses bjt op07 as driver with much higher input bias, but perhaps better drift.
I agree there is a high chance the bav199 diodes following the mux may not improve leakage below the mux leakage.
Also there is a chance dg508 is better than adg1208.
I just never tested it beyond some quick tests, to confirm that both were pretty good.
 

With a 10 mA test current one may want to have a way to turn of the current in case there is a significant foreign negative voltage. The SOA if the small SOT23 transistor is usually not that good. One may get away with a software solution, though not ideal.

The software solution for negative OVP, using the signal from Q615 isn't great.
perhaps the collector could just be used to pull the output p-fet gate up, to turn off?
eg. after the gate-resistor R606, maybe using a current-mirror to the +18V rail.

A buffer would anyway need a negative supply, as it would need to drive current at essentially GND level.

Thanks, that is a critical mistake. I was thinking about the op inputs at gnd, but forgot about the op being able to pull output to ground, without a dual-supply.

Switching to a lower output compliance voltage could be rather crude with transistor switching - this is not about precision, but only order of magnitude. There is anyway some drop at the protection.

Yes, just a crude ability to switch between say 2V and 10V would be enough.
I am trying to imagine would it might look like.
A zener or vbe multiplier/rubber diode to reduce compliance voltage would work well.
And better than messing with the static reference voltages at the lhs.
But I cannot see how to short-it/turn it off with a fet - without introducing leakage, maybe an optocoupler?.   
and if it is ground referenced, then it may screw up protection for over-voltages.

[Kleinstein]

The input bias of U603A is not critical at all. The current is provided by the drive side and not flowing through the range setting resistor. So it is only about drift and noise there. Somthing like an OP07 or more modern OPA207 is OK there.

The diodes in series with the MUX would only help for one direction of the leakage current, but not the other. The idea with the diodes in the 3458 and Keithley2002 is to use diodes to set the leakage instead of the MUX. One can than use a rather plain simple mux with higher leakage (e.g. DG408 or new TMUX4051) and also higher current capability. The 3458 even usus BJT switching incombination with the diodes. In my version I also use diodes for the middle ranges and a transistor instead of the diode for the highest current. So far I have not seen a leakage problem with the transistor and this way the 10 mA don't have to go through the mux.  Chances are the ADG1208 is good enough and can get away without the diodes. The fixed part of the leakage is not even critical. It is only the variable part of the leakage the would matter. This mainly the temperature effect as the voltages are fixed.

The somewhat critical parts for leakage are U603B, U604, U605 and D606.  If the series diodes with resistors to a auxiliary level are used U605 would be replaced by the diode leakage.
In addition there may be a buffer for the guard potential around the output / protection level.
Another point can also be relays. Especially the cheaper reed relays seem to be somewhat leaky.
Overall the leakage it not that super critical. There is no need to be much better than the normal voltage input.

The software solution for negative OVP, using the signal from Q615 isn't great.
perhaps the collector could just be used to pull the output p-fet gate up, to turn off?
eg. after the gate-resistor R606, maybe using a current-mirror to the +18V rail.

Such a system work, I have it in my circuit, with on the single PNP transistor. A current mirror would be even more controlled. I can use the auxiliary buffer that is there for the diode switching anyway, using the +18 V would likely be OK too.

For limiting the compliance voltage, one could also use the optional guard buffer and regulate / limit the there. This could be even relative accurate, though possibly a bit slow and tricky to get stable under all conditions. So there could still be transients with higher voltage.

[julian1]

I did some basic tests on current measurement functions.

Some thoughts on the design -

- high current relay K703 offloads the 1A and 10A ranges to shunt R702 (Vishay VCS301 0.1R 4W resistor) as soon as possible, so subsequent relays and copper traces can be smaller/thinner.
- the shunt/TIA select relay K709  unloads the capacitance of the shunt chain/switches from the TIA input, when the TIA is active.
- the high-current relays K702,K703 are latching RT424 and were tested for leakage, at least to 1pA level.
- BOOT2 used to bootstrap the protection is switchable depending on whether shunts or TIA are active.

The shunts drop 100mV.
So amplifier gain = 100x, except for 10A where gain =10x.
Excessive self-heating on the R702 for 10A may be an issue.
So 3A or even 1A (P=100mW) could be a practical limit, if the VCS301 doesn't have a heatsink.

The current shunts get switched using relays, while the sense taps are switched using analog-switch U703.
The spare relay pole could also be used to switch the sense tap.
But the analog-switch has an advantage as a precaution against extra Seebeck/thermocouple effects due to relay construction.
The 100x gain, means thermocouple offsets get amplified along with the small burden voltages.
On this point, relay K709 (shunt/TIA select) is shown placed in the shunt chain, after R702 where DCI-HI is sensed.
I think it should move before R702, to eliminate relay thermocouple effects, even if that would require changing to a high-current relay.


The TIA 10uA,1uA, 100n  ranges are stable with feedback caps of 22p.
Output range is +-10V.
A TIA has a large inherent dynamic-range. but range-switching is added using several feedback resistors.
This should reduce the Vos drift present in the measurement signal, compared with a fixed value TIA and switchable gain amplifier.
I am not sure if a chopper-stabilized op would work for ACI ranges (possible feature development), due to intermodulation distortion.
I have a preference to avoid zero-drift amps due to inexperience and high apparent complexity (high Ios/input offset currents, switch noise, emi source, one-time complexity).

Perhaps the TIA should be a compound amplifier, to help equalize BW across ranges, similar to the main amplifier.
But I am not sure if this applies to a TIA where current-gain is the important point, at least on the op-amp input side.
Also, bandwidth for different ranges, can be somewhat controlled for - with the value of C in the Rinput/Cf ( 10k/22p=723kHz ).


The input protection has not been tested.  A single bridge-rectifier repackage (gbj1508) would be simpler than discrete dpak bjts and smb diodes.
It would probably be better to demonstrate that the more complicated circuit with BC tied bjts is needed before using it.

I am not sure if some inductance should defined on the input near the input fuse.
Or whether the inductance shown in some schematics is added as a workaround for small dimensioned fuses blowing on transient currents.

[Kleinstein]

K709 should indeed be moved to before the whole shunt chain starting with R702. It is not so much because of thermal EMF in the relay but because of contract resistance that would be included too.

The 0.1 ohm shunt is OK for 1 A, maybe 2 A with a few thermal effects. I would not expect much more than that. It is more that one uses even less than 100 mV burden for higher currents to keep the heat low.

Nomally the main amplifier as used for voltage could also be used for the shunts, especially for the higher currents. With the still relative low resistance there would be no issue to use an exra AZ amplifier (e.g. OPA189 oir OPA388), but as the JFET stage for the voltage mode is really low noise, there is not real need for this.
For the low currents it is natural that they get slower. A compound version (a little similar to the 2 OP-amp integrator) may be an option if one wants to use an AZ amplifier at the TIA too. This would allow to use a slow AZ OP with 5 V supply combined with a faster FET type to still get a full +-10 V output. This would mainly be a thing if the TIA is also used for slightly larger currents.

[julian1]

Edit. sorry deleted and reposted.  I may have misunderstood Kleinstein's comment. Using larger current resistors, with +-14V may be preferrable.

For the integrator input it looks like the plan is for 40 K at the reference and 50 K for the input - just like the HP3458. This would give an about 14 V FS range, but may result in more gain drift from the switch resistance. I would expect an extra   -1 ppm/K from this. So not very much, but avoidable. It also increases the resistor noise a little over the case with 3 x 50 K or 3 x 40 K. Using a +-14 V ref instead of +-12 V as in the 3458 is the better alternative to the lower resistors for the references.

I already noticed differential heating effects from switch resistance with +-14V and 3x40k in the past.
So it is marginal.
Some ways to address this are - to parallel the '4053 switch which would double charge injection, or drop the ladder voltages - eg. to +-12V or lower.
There are a couple of ways to do the divider ladder.
A 3 resistor divider is simple but doesn't map well into combinations of fixed value arrays (4x10k, 4x50k etc).
A 4 value resistor divider needs gnd current compensation, or else another op to buffer the gnd.

I am tempted to try discrete smd z-foil instead of thin-film arrays, because TC tracking is probably good enough.
They are not generic, however the flexibility to change values and experiment as needed would be really nice. Also inexpensive non-prec resistors can be used for some tests.
Cost is not too different.
Is there a better approach?

Has anyone tried vertical in-line stacking of smd resistors to minimize temp gradients, to see if it improves TC tracking?
z-foil datasheets show a typical TC parabola (Fig 3. vmsp datasheet), but it is not clear in what direction it might shift for individual resistor samples.

[Kleinstein]

Getting a +-12 V reference to get essentially the same configuration as the 3458 is not that attractive. I consider this more like an oversight and strange choice already for the 3458.
It would be better to change to 3 equal resistors (e.g. 3 x 50 K or 3 x 60 K) for the integrator. The resistance of the switches has a high TC (some +6000 ppm/K). Even combined with some 2000x higher series resistors this still contributes some 3 ppm/K. To get good matching for the overall resistance it helps to have the the same resistance. A 20 % difference is not dramatic, but still adds some error to the matching.
The other point is that there is additional noise gain, when the resistors for the references are smaller. So 3 x 50 K is not only easier but also lower noise. With equal resistors at the integrator the reference amplification is easy and can use 4 equal resistors for a +-14 V range reference and some +-13 V range.

For the ref. amplifier the choice of 3 resistors as a single chain or separate gain and inverter is a balance. The version with a single chain adds noise from the 2nd OP also effective to the reference voltage. On the upside it needs less current or could use smaller resistors with the same power consumption. I don't consider it a big difference and either way can work.
The resistors as shown with some 2x10 K at the inverter make about sense. These resistors also add to the noise and OP-amps like the OP27 really like a low source impedance. So I would more prefer somethink like old style OP07, OPA207 or cheap OPA202.

The resistor value at the integrator is a compromise: lower resistors give less noise, but more INL.  I have 50 K as this is available as array. A bit more would not be that bad. The extra noise is like having 2 x the resistance in series to the input signal. The 50/40 K combination of the 3458 has about as much noise as having 3 x 56 K for the resistors and a little more noise from a few other sources. So 60 K or 70 K should still be OK.

The INL effect is 2 fold:
1) self heating of the resistor : here having 40 K as 4x10 K in series helps to spread the power and with good matching this should not be an issue.
2) nonlinear R_on with the MOSFET switches: this is not a thermal effect, but more adding half the voltage drop across the channel to the effective gate voltage. Here the quality of the resistors does not matter. 40 K may still be OK, at least for the start.
If really needed one may mix 10 K and 20 K resisor arrays. The MORN type should fit on a LT5400 footprint, just without the thermal pad.

With 3 seprate resistors the INL part is not about TC matching but about the TC of the resistor for the input. Tracking only applies with rather tight thermal coupling. For the ref. amplification TC matching would still apply. If really needed there are even 5 K BMF arrays in a SO8 case, though I would consider them overkill.

So far the TC matching in the resistor array I have tested (NOMCA and ORN) seems to be quite good. From the gain vs temperature I got better than 1 ppm/K so far for temperature close to roomtemperature. The TC specs are for the whole range including the tricky low value resistors. Chances are the ORN arrays  have a worse TC matching specs than the similar MORN type mainly because the ORN series also includes lower values. The 5 K / 50 K resistors used in the ADC are the easier and thus usually better ones.

[julian1]

Thanks Kleinstein,

I may have got stuck in my thinking, because past tests showed integrator noise correlated very closely to resistor value choices.
Changing from ref=2x40k,sig=80k to ref=2x40k,sig=40k halved the measured integrator RMS noise.
Then changing to ref=2x40k,sig=50k to try to reduce heating, and fix INL, increased noise proportionately.
So the schematic values of 40k and 50k shown were a compromise to juggle noise and inl/heating based on past experimentation, rather than match HP design choices.

But, maybe these results were entirely down to the choice of lt5400.
Switching from lt5400 to morn without other change, significantly improved noise - perhaps so that other factors now dominate.
And this is consistent with your experience.

So it would be good to evaluate higher values - 3x50k or 3x60k .
And using +-14V for references, makes using resistor arrays easy as you note.

[Kleinstein]

Normally the LT5400 should be low noise. A point where the LT5400 is not that good is the extra capacitance to the thermal pad and between the resistors. When fast switching is used this capacitance can add noise. Unless super fast modulation is used this should still not be very much.

With 3 equal switching the natural choice really is to also use equal resistors and than a +-14 V ref makes sense.
The main question remaining is what resistors to use. 50 K works well for me and is available as arrays, which makes it the logical choice for a simple version.
With 3 x 100 K the noise would be relevant and hardly a chance to reach the noise level of the 3458 anymore.
The noise from the 50 K resistors corresponds to some 290 nV for the 1 PLC AZ mode. A significant noise source, but still a bit away from the 500-600 nV noise level of the 3458.
There is a little noise from the switch capacitance that also scales with the resistance, but this should not be very large with the low capacitance LV4053 switches unless swithching is really fast (e.g. >300 kHz). The 50 K / 40 K resistor combination in the 3458 already contributes some 306 nV - so less attractive.

Slightly larger resistance like 60 K (e.g. 3 x 20K) should be noise wise still OK (e.g. some 320 nV of noise contribution).  Already combining a few resistors smears out the heat and each array sees less heating and chances are that matching can be better from statistical averaging. It is not so much the slightly larger resistance, but also less thermal resistance that helps. With the LT5400 40 K = 4x10 K should be OK too due to the low thermal resistance and good matching. The question there is more the U² part from the nonlinear switch resistance - unless the front end compensates for this by using positive and negative readings.

[julian1]

I added a second channel mux/pre-charge switch.
The idea here is to apply the same input switching strategy to alternative HI inputs, to improve 4-phase sample cycles.
This should work for ratio-metric mode (alternate dcv-hi, 4w-hi).
As well as for AG mode (alternate dcv-hi,dcv-source ) and should support an amplifier configuration option using jfets with high thermal effects/walk (if3602 ).
Another possibility would be alternate sampling of voltage and current inputs, although it's not clear how useful this is.

After adding the extra channel, it is interesting to see the extra symmetry created in the input section.
There is the possibility to use the second channel to also mux isolated LO inputs (eg. DCV-LO, 4W-LO) - even just for test purposes.

A further possibility would be to make the gnd-referenced node selectable.
A divider can create a CM node between the buffered boot hi/lo inputs.
And if this CM node is gnd-referenced via a selection relay, a differential voltage-range is avaliable with twice the input range.

If I understand correctly, Kleinstein has discussed this approach, and does something similar,

  https://www.eevblog.com/forum/metrology/diy-high-resolution-multi-slope-converter/msg3827432/#msg3827432

I think LF noise from the channel buffers, will be added when sampling in this differential mode.
But this noise ought to be mostly cancelled by the AZ zero subtraction.
In addition, the mode would only be used/useful when amplifier gain=1.

Does this approach makes sense?

The additional complexity once the second-channel precharge switching/ mux for RM, AG modes has been added, seems low.
It looks like it just needs an extra relay and divider.
And maybe some changes to the input protection.

The question there is more the U² part from the nonlinear switch resistance - unless the front end compensates for this by using positive and negative readings.

A single DPDT relay/or mux could invert the inputs, to support taking measurements in both polarities.
This would ease turn-over tests from external (isolated) input dc sources, and might be justified on the basis that it is a good check for measurement confidence.
But the switching action couldn't be performed per-cycle, without disturbing the inputs, unless they were tapped after the precharge switches.
And then it gets complicated with the gnd-reference.

[Kleinstein]

A second input can make some sense. However for the 2nd input I see relatively little need for the extra MUX in front of the pre-charge circuit. There should already be plenty if input paths available.

I see a limited use for the divider between the 2 guard (buffer of the inputs) signals. The relay to link the the circuit star ground makes no sense as the amplifiers are from the same supply anyway and one would only load the amplifiers differently.

Doubling the range in a differential mode is not linked to having a 2nd input. The idea for doubling the range is driving the low side terminal, so that the ADC can read +U/2 from the input and -U/2 from the low side. So the AZ cycle is not switching between signal and zero,  but a positive / negative type chopping.
The circuit is by using an inverter (with low pass function for stability) from one guard signal and use this to drive the low side terminal.  To have the doubled range also for the other signal one would need to switch which guard signal to invert or have a 2nd inverter and switch after that.  One would still have the doubeld input range only available for 1 input at a time and the other input has to use the protection part (FETs with PV OK for control) to isolate the unused input, as otherwise clamping (and thus more input loading) can happen early. The low side signal would go to the main mux, but no need for a precharge part for the inverter output.

To still have the normal mode available and especially for the amps part it would make sense to have a relay at the low / COM terminal to switch between the circuit ground (as the classical connection) and the driven low side from the inverter.  If there is no extra protection at the inverter output one would also need isolate the current input, which would be a 2nd low impedance path. So the relay should switch both COM and the current input.
The idea for protection is to have only 1 unprotected path - classically ground, but it can be another low impedance signal as well.


In the current amplifier configuration (amplification relative to ground) the differential mode with the driven low side is mainly useful for a ~20 V range. Already with an amplifier gain of 10 and thus a 1 resp. 2 V range the inverter to double the range is a 2 sided thing: it still doubles the range and can help with INL, but the noise of the inverter is relevant. So the 2 V range would be possible, but more noisy than the 1 V range.  The noise of the inverter enters with the same frequency band as the main amplifier (e.g. around 25 Hz for 1 PLC operation). It is not so hard to make the inverter lower noise than the ADC and accuracy of the inverter is not critical. Still the main amplifier is usually lower noise than the inverter (from the resistors alone).
My current configuration (in the link to the other thread) is a bit different and needed the AZ type main amplifier.

With the extra inverter to double the range the ADC alternates between U/2 and  -U/2. This helps with even oder INL contributions, but is still not a turn over test, as it depends on the quality of the inverter and the ADC offset. The inverter is still not that critical as even a case with +0.6 U and -0.4 U would still suppress the even order errors quite well and not reduce the range very much.
One gets a limited INL test by comparing the result in the classical 10 V mode and differential mode. E.g. with 10 V at the input one has 10 V and 0 V compared to some 5 V and -5 V.

To support a turn over test and also the more general sum of 2 voltages type one could add switching for a choice of 2 low side terminals and than also use the 2nd input path. For the turn over test one has then U1+low2 and U2+low1 externally connected in parallel.