DIY high resolution multi-slope converter

[Kleinstein]

It may not that bad to add a µC/control connector to the ADC board, even though I would likely not use it.

I had a look at my planed new PCB / circuit and realized that most of the signals that the µC connector would need are anyway planed as test-points.
The minimal version could get away with some 14 pins.
My current plan has 6 more direct signals for the front-end and 3 additional signals for the ADC to allow some optional extension there. So it would be overall some 24 pins, likely split in 3 parts on different sides of the µC footprint on the PCB.

The modulation frequency for the run-up is compromise. Fast modulation reduces the error from dielectric absorbtion and allows for a faster run-down. It also helps to keep the capacitor small and this way helps with residual charge noise (can matter with fast conversions - less with 1 PLC and rarely with 10 PLC).
One the other side fast modulation make jitter more relevant (noise resulting from jitter goes up with the square root of the frequency), leaves less time for the integrator settling and amplifies INL errors from switching artifacts (can be proportional to the frequency and more if less settling time is used). So there is also some incentive to keep the frequency relatively low, if one does not need high speed. 
For testing one can compare different frequencies. This gives a hint how much noise is from jitter and if INL effects are DA related or switching artifacts.

The µC signals should have jitter well less than 1/2 clock period. So 20-100 ns jitter would be a bit on the high side, but 5-10 ns could be OK.
For direct use with the input switch <1 ns would be nice and this is still not demanding (chip internal PLLs may be OK ).

[iMo]

.. I used the 20-100ns jitter/prop_delay in my above motivation post as an extreme (but still working) example. In reality the jitters/prop_delays over reasonable number of connectors and reasonable lengths of wires will not be higher than, say 10ns, no way more, IMHO.. 

PS: and again - when needed a ps or ns precise timing simply do use an FF placed on the ADC board (fed by the quality master oscillator, say, 50MHz one placed on the ADC board close to the FFs). Then you may have even those extreme jitters/prop_delays between the ADC board and MCU/FPGA there, absolutely no problem, IMHO.
You may also place some 50MHz master clock distribution drivers/buffers on the ADC_board feeding the MCU board. No problem with jitter/prop_delays there as well. But all those FFs (placed on the ADC board) shall be clocked by the 50MHz master oscillator (placed on the ADC board) directly with short and equally long tracks..

PPS: btw., all MCUs, afaik, use "synchronisers" at their inputs, so there is an inherent delay of 2-3clocks. So the design shall not rely on the MCU's i/o timing (not counting the large internal noise modulating thresholds mentioned above). The same with FPGAs - good designs use usually the synchronisers at the inputs too (where applicable). With the interrupts the same - they introduce large unpredictable jitters/delays as well. So ints should also be not used when talking about precise timings..

Another option (a better one, indeed) is to use a, say, 25MHz quality oscillator (the master clock) on the ADC board, feed that 25MHz master clock upstream to the MCU board, and there the MCU/FPGA will use it locally as the input to their PLL module (I think the internal PLL modules have usually the input freq limited to some 25MHz or so). Then you may multiply the master clock inside the MCU/FPGA such you get any applicable MCU/FPGA clock. With the concept with the FFs placed on the ADC_board the PLL jitter or some clock phase shifts/delays against the 25MHz master clock do not matter much. And you may run your MCU/FPGA on XXXX MHz and play Doom while doing 300kHz MS.
 

[miro123]

Ok, it is "almost" clear. 🙂
The common-sense rule is that the delay (including jitter) must never come close to the active edge of the flip-flop clock. For example, if the ADC clock is 25 MHz, a delay of 39.99 ns with only 11 ps of jitter puts you back in the lottery game. Higher  of 50ns is safer in this case

Clock distribution ICs are generally overkill for an application like this. Mostly they consumes a lot of power and introduces no delay my phase jitter

I am curious about the reason for this non-traditional approach. Even back in the 1980s, HP, Keithley, and Fluke typically placed a dedicated guard CPU, FPGA, or ASIC on the ADC board, and I can think of at least ten reasons why they did so. In my opinion, putting the voltage reference on a separate board makes much more sense.

[MiDi]

Coming back to the noise measurements https://www.eevblog.com/forum/metrology/diy-high-resolution-multi-slope-converter/msg6316302/#msg6316302

Some thoughts on jitter induced noise:
The 3458A has around x10 modulation frequency in comparison to run-up W (slow) and both have compareable noise levels.
An A3 replica with off the shelf 20MHz oscillator and original U180 did not show significant difference in noise compared to original A3.
The "best" NU180 have significant higher noise, iirc x1.5 than original U180.

My conclusion (correct me if I am wrong):
- XO is not the main contribution to jitter induced noise
- off the shelf D-FF & switches can perform reasonably well with high modulation frequency
- scaling run-up Q around x1.25 noise than W to 3458A modulation frequency would give near x2 noise
- there is a "major flaw" in current implementation around the D-FF & switches

Any suggestions how to identify/encircle the cause?

[miro123]

My conclusion (correct me if I am wrong):
- XO is not the main contribution to jitter induced noise
- off the shelf D-FF & switches can perform reasonably well with high modulation frequency
- scaling run-up Q around x1.25 noise than W to 3458A modulation frequency would give near x2 noise
- there is a "major flaw" in current implementation around the D-FF & switches

Any suggestions how to identify/encircle the cause?

Thanks Midi I think you hit the nail on the head. I fully agree with all four bullets.
Question - switches are connected around integrator virtual ground - it bounce some hundreds of mV - positive peak does not border me but what about negative?
8 1/2 digit project uses switches powerred and controlled at +-1,25V.As far as i remeber the  forum member Macaba did some investihation.

Question - Does changing to the faster opamp in integrator makes noise lower - e.g. instead of OPA140+ OPA140  go to OPA140+ OPA1655 or OPA828. Faster opamp should make the VGND jumps shorter  https://assets.zyrosite.com/AwvLzKbyDqfJn2B8/22rpt02-true8digit-deliverable-d4-P1OmTBOuSeMgWcfm.pdf

[Kleinstein]

Unless one wants super fast conversions, there is no real need to have the modulation as fast as with the 3458. With a good capacitor there is no real need to go higher than some 30 or 50 kHz. Slower modulation helps not only with noise (less sensitive to jitter and the capacitance at the switch), but also with less INL from when the switching is not ideal. The capacitance effect should be small and the LV4053 are already relatively low capacitance.

Not all XOs are the same when it comes to jitter. Quites some should be good enough, at least when the modulation is not super fast.
The 3458 has some ferrite in the clock path. Some other fast circuits, e.g. the KS34410 (with rather fast modulation - so they should care about jitter)  have resistors in the clock part.  A point that could be an issue is the µC acting back on the clock. Ideally there would be a buffer in the clock going to the µC. I don't know if the board has such a buffer.

With my STM32 version I remember less effect from the modulation frequency. This is with AC74 flip flop and a 3.3 V XO (nothing special though).
On the other side the overall noise is not much lower, likely with some noise from the DCDC converter.

I would not expect a faster OP-amp at the integrator to help with noise - it is more a thing against more systematic errors and thus non-linear effects from timing effects or the integrator settling.  Slower modulation should also allow getting away with a slower integrator as the short pulses can be longer.
I don't remember getting that large pulses at the virtual ground - compared to the 8 1/2 digit project the larger capacitor at the integerator could make a difference. Up to some -200 mV the LV4053 switches should be reasonable OK and parasitic diodes not engage.

[MiDi]

Question - Does changing to the faster opamp in integrator makes noise lower - e.g. instead of OPA140+ OPA140  go to OPA140+ OPA1655 or OPA828. Faster opamp should make the VGND jumps shorter  https://assets.zyrosite.com/AwvLzKbyDqfJn2B8/22rpt02-true8digit-deliverable-d4-P1OmTBOuSeMgWcfm.pdf

https://www.eevblog.com/forum/metrology/true8digit-project/msg6263264/#msg6263264
&
https://www.eevblog.com/forum/metrology/true8digit-project/msg6299466/#msg6299466

Unless one wants super fast conversions, there is no real need to have the modulation as fast as with the 3458. With a good capacitor there is no real need to go higher than some 30 or 50 kHz. Slower modulation helps not only with noise (less sensitive to jitter and the capacitance at the switch), but also with less INL from when the switching is not ideal. The capacitance effect should be small and the LV4053 are already relatively low capacitance.

Not all XOs are the same when it comes to jitter. Quites some should be good enough, at least when the modulation is not super fast.
The 3458 has some ferrite in the clock path. Some other fast circuits, e.g. the KS34410 (with rather fast modulation - so they should care about jitter)  have resistors in the clock part.  A point that could be an issue is the µC acting back on the clock. Ideally there would be a buffer in the clock going to the µC. I don't know if the board has such a buffer.

With my STM32 version I remember less effect from the modulation frequency. This is with AC74 flip flop and a 3.3 V XO (nothing special though).
On the other side the overall noise is not much lower, likely with some noise from the DCDC converter.

Today the strength of MS converters is more in the slow sampling regime, there are excellent fast ADCs available (e.g. the AD4630 family), so no need to push sample rate like 3458A back in the 80s.
3458A is good for comparison to show how even fast modulation performs and get a rough estimation for scaling with slower modulation regarding noise & INL.
From the results my conclusion would be that the optimum is with even slower modulation than W and higher integration capacitance.

Coming back to "noise scaling" Q vs W:
The clock distribution would not be my first suspect, CPLD & U180 in 3458A share the raw output of the XO, only filtered by two ferrites.
Iirc you already did some investigation around the XO and there was only minor changes, right?
Exchanging the D-FF with an AC74 type sounds like an easy test.
Exchanging the switch with the same type as in NU180 requires some patching, but may allow better comparison.
What about a comparison between the different run-up modulations available, could that narrow down the source?

Could you please post your noise measurement results with internal short for your adcs?

[Kleinstein]

I don't think the AD734 or similar as used in the NU180 are such a good choice. They have a separat negative supply, and thus an extra level shifter stage, while the LV4053 have only a single ground. In addition the capacitance of the AD734 is on the high side.

The PCB with the AVR and SMD FF may already have an 74AC (or very similar 74VHC, 74AHC, 74LV) flip flop. AFIR my board still has a 74HC (did not have AC in stock when adding it), but it's not easy to check for me as it is mounted dead bug. It could be a simple test for me to see what the upgrade brings.
From memory the noise with the FF was about the same as directly from the AVR. From memory I got a little below 500 nV noise for 1PLC AZ mode with the slow modulation and somewhat more with the faster (normal) one.
My current STM32 based version gets some 480 nV with the internal zero (without the input amplifier, but still the buffer) and some 500 nV with the input amplifier. The modulation is at some 61 kHz. I may have to recheck the effect of a different modulation frequency there - with my initial tests I still had more extra noise from the DCDC part.

A modulation frequence much below 30 kHz may be where the INL from DA can become visible (at least at 1 PLC). With extra measures to reduce that error, a lower modulation frequency (like 10 or 20 kHz range) may indeed give lower noise and maybe better INL.

Attached are Allan dev. curves with short at the input. The non AZ case is from the same measurements, just looking at half the data  and not taking the difference. A true non AZ mode could be 2 x faster.

[miro123]

I have been running the MS integrator simulation and the following question popped up.

Why the precision OpAmp is powered from +-15V? I think that even +-2,5V is more than enough. Lower power means lower dissipation.

[Kleinstein]

Powering the precision OP-amp in the compound integrator from a lower voltage is OK and it may give some advantage. With my circuit the 5 V are from the same transformer winding and are mainly used for the digital part and thus may not be as clean.
The OPA140 and related need quite some (3.5 V) headroom on the positive side. So +-2.5 V would not work, but -1 V and +5 V would be OK.
The precision amplifier does not see much load, so a higher voltage would no be that negative.
Especially an AZ amplifier could well use +-2.5 V or similar. The same is for a low power version.

[GigaJoe]

I have been running the MS integrator simulation and the following question popped up.

Why the precision OpAmp is powered from +-15V? I think that even +-2,5V is more than enough. Lower power means lower dissipation.

It transistors , Sir..  Take a basic building block, diff. cascade , even with a current gen.  parameters would be differ between ±15V and ±2.5V
there is many blocks inside opamp that behave differently when the rail voltage differ.
Synthetic models usually not care about , simply feed it ±100V , and it fine , stuff working
If you open PDF some defined parameters for specific rail voltage, and it differ ..  usually best at maximum , as it initially design in mind as max rail,  transient a bit faster, electrons runs faster   and so on.  At low voltage - it more like feature, not an ideal run.
Reason why a lot ±2.5V  exist. 

[Zondar]

I don't think the AD734 or similar as used in the NU180 are such a good choice. They have a separat negative supply, and thus an extra level shifter stage, while the LV4053 have only a single ground. In addition the capacitance of the AD734 is on the high side.

Assuming CMOS switches ("transmission gates;" parallel P and N transistors), and given that in the 3458A the output is ~0V potential:

* With Vss=0V, the N-channel transistor does all the work, and the P-channel transistor is dead weight, as it never even turns on. It gets worse, as most of the switches people have looked at strive for good on-resistance flatness. That leads to the P-channel side's W/L being made considerably larger than the N side (e.g. by the difference in mobility). That means that the capacitance could be 3+ times higher than if only an N transistor was included, and charge injection could be worse too.

* With Vss=-0.6 (as in the 3458A), the P-channel side will likely conduct, but not strongly. Some utility is gained, with effects closer to the Vss=0 case.

* With Vdd=2.5, Vss=-2.5 (or similar): Both transistors are about equally on, carry about equal current, and with about equal but opposite flatness. Charge injection may be lower. This operating region should have the lowest on-resistance and best combined flatness.

I'd say either run a CMOS switch with split supplies or, to go "full audiophile" at 0 or -0.6V, look for low-voltage, low-power, pairs of n-transistors. 

[Kleinstein]

The analysis that the P channel FET is not helping is correct.
The TI SN74LV4053 data-sheet does not show charge injection or R_on curves, but some similar part do. They tend to give lowest charge injection in the 0-1 V range. From my measurements the charge pulse from switching is not too large.
A -0.5 V or similar supply may be an option, though extra effort, even though it can work without level shift for the logic.

Ideally one would have some kind of N-mos only switch, but these are rare. The only common types seems to be DG611-613 and these are for some 15 V supply, with level shift and not very fast. There would be discrete N-mos switches like the SD211, but these would also need an extra drive with break before make (a AC74 FF seems to switch both outputs together and would have essentially no delay - it is still used in the  R6581).

I like the LV4053 as it work well and it easy avialable (even DIP as used in the first tests) and cheap. Despite of the loose specs, I had low leakage too.

[mawyatt]

Assuming CMOS switches ("transmission gates;" parallel P and N transistors), and given that in the 3458A the output is ~0V potential:

* With Vss=0V, the N-channel transistor does all the work, and the P-channel transistor is dead weight, as it never even turns on. It gets worse, as most of the switches people have looked at strive for good on-resistance flatness. That leads to the P-channel side's W/L being made considerably larger than the N side (e.g. by the difference in mobility). That means that the capacitance could be 3+ times higher than if only an N transistor was included, and charge injection could be worse too.

This is true as we found while developing the PolyPhase Mixer (PPM) way back. A single NMOS device as a ~0 volt "switch" significantly outperforms the classic P and NMOS "analog" switches wrt to on resistance and parasitic capacitance. Also we found and confirmed by other researchers the 3rd order products produced by the inherent non-linearity of the MOS switches is significantly lower with NMOS utilizing the same silicon area. 3rd other non-linearity is usually the most significant issue at RF/MW/MMW type systems, and critical for the PPM developments. We also found that "Triple Well" NMOS was the overall best, altho many CMOS processes don't support Triple Well devices. Details on the PPM here if interested:

https://www.eevblog.com/forum/rf-microwave/polyphase-or-n-path-mixer/msg5753297/#msg5753297

Best   

[Zondar]

It's true that suitable individual transistors are hard to find. Perhaps the 2N7002 might be a starting point. R_ON = 3 Ohms, C_in=5 pF, gate to drain charge = 0.17 pC. Not ideal, but not too bad and certainly better than most.

Given the overhead (break before make, increased capacitance from multiple packages, etc.), it's probably the case that one of the available CMOS switches is more practical over-all. But I'd caution against too-quick presumptions about "extra level shifting" or tri-state outputs, etc., prior to actual testing. There are too many other factors in play, e.g. 1970's vs. 2020's technology. And if CMOS is used, you really do want that split supply.

[MiDi]

TC & drift of K1, K2 and SF.
K1 & K2 measured in mode L, SF measured in mode A (internal Reference, AZ, runup W, 1 PLC) each alternating for 1min for nearly 5 days.
The temperature sensor TMP119 was floating near the bottom of the PCB.
The TC linear fit uses a robust multi-scale difference method and includes an adaptively smoothed term to account for slow drift over time.

[PCB.Wiz]

It's true that suitable individual transistors are hard to find. Perhaps the 2N7002 might be a starting point. R_ON = 3 Ohms, C_in=5 pF, gate to drain charge = 0.17 pC. Not ideal, but not too bad and certainly better than most.

Generic 2N7002 vary a lot by vendor.

The lowest Cap specs are seen on new parts like Nexperia 2N7002AK-Q & BSS138AK-Q, (same C-V curves lower Vth) and maybe ROHM RU1C001

[Kleinstein]

The 2N700x and BSS138 would be rather high gate capacitance. This gives a larger gate charge spike (charge injection) and capacitance at the switched node that adds to the noise. So more like look for C_gate < 10 pF. R_on in the 10 ohms range would be no issue and with gate voltage modulation even 50 or 100 ohms could be OK.
If looking for discrete MOSFETs, i would be more something like SD211 or a SSM6N16 (comes as duals).

[PCB.Wiz]

If looking for discrete MOSFETs, i would be more something like SD211 or a SSM6N16 (comes as duals).

?
The SSM6N16 has higher Ciss Coss numbers than the new parts I mentioned above.

[MiDi]

Test results with D-FF U17 AC74 instead of HC74 (switch control):



The faster AC74 shows higher noise than HC74, so that goes into the wrong direction.
If the noise is independent this would be around 50nV additional noise introduced by AC74.
No significant changes in the deviations from W (slow) < Q (normal) < P (fast) visible.
Conclusion: no significant influencce of D-FF on the differences between W/Q/P?

Adding 100nF on switch U5 between VDD and VSS and 1µF parallel to C27 for U17 FF lead to slightly higher noise (but might be inside measurement uncertainty).
What to try next?

Attached the details of the runs wih W/S/Q/P/R/V, 1+4 PLC, GND/7Vref in mode B same run-up (non AZ).

[Andreas]

Adding 100nF on switch U5 between VDD and VSS and 1µF parallel to C27 for U17 FF lead to slightly higher noise (but might be inside measurement uncertainty).
What to try next?

Hello,
a 1uF (ceramics?) may lead to oscillations together with C27. I would use a 10uF Tantalum (3 Ohms ESR).
R26 together with 14 Ohms output resistance on AC74 looks odd to me. I would rather use a Ferrite bead for R26.

with best regards
Andreas

[Kleinstein]

There are a lot of data to look at.
The noise looks a little like there is still some popcorn like noise, though this looks similar for the different modulation frequencies.
So chances are this is not jitter related, but more an amplifier or resistor.

The noise is still quite a bit higher with the faster modulation. This does point to noise from jitter or the switched node capacitance. Even though the layout has a bit extra capacitance, I don't see the capacitance that large to cause it.

In the schematic, the ferrite at pin 7 of the LV4053 is a bit odd. It is not so clear how pins 7 and 8 are used for the ground in the LV4053 (Ti shows both as GND, NXP has them a bit seprate for the input and actual switch part. For the switch itself the ferrite may have some justification, but for the input signal it can add jitter. So maybe try with direct ground to pins 7 and 8.

I agree with Andreas that a 2nd parallel MLCC can cause a resonance and may give more ringing. So a tantalum would be better.
A ferrite bead instead of R26 could make sense, but they can also have ringing. So the option could be resistor and ferrite bead in parallel.
The supply current to the FF should still be relatively constant (5 V*35 pF*16 MHz ~ 3 mA ). So 10 ohms give not that much drop.

A possible other point to test could be adding some series resistor (e.g. 20-60 ohm) in the clock towards the µC. This would be to reduce loading to the oscillator and reduce the chance for the µC to effect the clock. It may also dampen ringing (higher harmonics resonating with the trace as not terminated transmission line), even though the trace is still relatively short.  The faster 74AC74 would react a bit more to the fast ringing part.

[MiDi]

Additional tests to determine the root cause of the rising noise with rising modulation frequency.
Measurements: 10-minute captures, internal zero and internal ~7 V reference, six firmware modes, 1 and 4 PLC, three visits per condition, K1/K2 and residual-ADC scale-factor calibration preceded the measurement campaign
Modes S/W, V/Q/R and P use nominal pattern frequencies of 34.5, 69 and 138 kHz. S doubles W’s comparator-read rate. V/Q/R use long/standard/short fixed phases (1.50/1.00/0.67 µs).
These tests are not intended to improve the adc in the first place (some lead to worse TC/Drift and INL), but to gather knownledge of the effects of the modifications on noise performance.

Schematic at the starting point:


Comparison of consecutive campaigns

2026	Plot label	Change	Observation / reference	Significant change	Implication / what remains open
21 Sep	Original	U17 HC74; earthed enclosure	Baseline; S/W < V/Q/R < P.	Baseline
22 Sep	+Caps	U17 +2.2 µF; U5 +100 nF	Small, mixed changes vs 21 Sep.	-	No demonstrated benefit of these added capacitors
23 Sep	FB shorts +Caps	FB1/57/102 bridged; both added capacitors retained	NSD +26–92% vs 22 Sep.	Large increase; 18/24	Reference/return-path impedance is implicated, individual beads remain unresolved
25 Sep	New FB	Bridges removed; FB35/57/102/103 replaced with the same types due to damage	Similar vs. 22 Sep	-	Just confirms same noise vs. 22 Sep. after replacing damaged FBs
26 Sep	Battery	ADC: 2 × 5S Li-ion; Pi: powerbank. Ethernet disconnected	Mostly modest changes vs 25 Sep.	-	No isolated supply or communications effect. Only improvement is missing noise bump around 5Hz
27 Sep	FB shorts, battery	FB1/57/102 bridged; U5 extra 100 nF removed.	NSD +15–97% vs 26 Sep.	Large increase; 11/24	The high-noise state also occurs on batteries, Mains supplies have no significant effect
28 Sep	FB1 only	FB57/102 restored; FB1 remains bridged	NSD −17–46% vs 27 Sep; dropout omitted*	Large decrease in 2/18	The return toward lower noise while FB1 stays bridged points to FB57/102 or their interaction. The battery drained into to low level and the regulators dropped out of regulation at some point, those results are omitted
29 Sep	GND/LAN	Additional GND wire U17.7–U5.8; Ethernet reconnected.	Modest/mixed changes vs 28 Sep.	-	Wire and Ethernet effects are insignificant
30 Sep	U5 22Ω	Four series 22 Ω at U5 pins 1/2/12/13.	Zero-input estimates 3–16% lower vs 29 Sep.	Small decrease; 3/24	Analog switch-path impedance affects the result. Damping, return-current coupling and settling remain possible explanations
2 Oct	Sync 22Ω	22 Ω in each U17 select output.	NSD changes about −3 to +2% vs 30 Sep.	-	No demonstrated benefit from this select-resistor change. It does not exclude internal timing variation or every edge-coupling mechanism.
4 Oct	R/C	10 kΩ LT5400 elements parallel each 25 kΩ RN202/203 element; C11 ×3.5 to ~7.7 nF.	Lower zero-input estimates vs 2 Oct; incomplete repeat coverage.	Large decrease; 5/20 repeated conditions*	Resistance, current, capacitance and loading change together. Thermal noise and dynamic transfer cannot be separated. Drift was still quite high, so the measurement was repeated next day
5 Oct	R/C repeat	Unchanged	No resolved additional improvement vs 4 Oct. Zero remains 19–27% lower vs 2 Oct.	None vs 4 Oct; 0/20*. Large decrease vs 2 Oct; 9/12 zero conditions	Repeat supports the lower-noise R/C state
6 Oct	Mains PSU	Pi and ADC both returned to mains supplies	21/24 estimates higher vs 5 Oct; ΔNSD −2.54 to +9.73 nV/√Hz.	-	No significant impact of PSU, other than the additional bump around 5Hz

* For 28 Sep. comparisons: six PLC4/+7 V dropout conditions are excluded.
Comparisons involving 4 Oct have 20 conditions with repeated captures, three single-capture comparisons and one missing condition.
The three single-capture results are not used for the repeatability-based significance labels.


Figure 2. NSD comparison 0.5-4Hz all states. At 1 PLC/zero, W/Q/P changed from about 93/114/164 nV/√Hz at baseline to 67/78/105 in the R/C repeat.



Figure 3. Changes relative to Original, not to the preceding campaign. The two bridged states stand out. Negative ΔNSD means lower noise density, it is not the amplitude of a removed noise source.



Figure 4. S/W stays near one and V/Q/R remain close while the frequency families remain separated. This weakens comparator-service rate or fixed-phase duration as a complete explanation.



Figure 5. W spectra retain the low-frequency rise and the larger +7 V background. The feature near 5 Hz is from interaction of mains frequency entering via the supplies.



Figure 6. Digital postprocessed pair subtraction at zero: z[k] = x[2k] − x[2k+1] aka AZ.

The 3458A curves are all NPLC1, LN mod/stock are different devices, in Figure 6 the 3458A curves are native AZ measurements, while DIY curves use synthetic pair subtraction.


Ideas for further investigations (clock to µC buffer is currently running)

• Separate the ferrite paths FB57 and FB102 individually (divides impact from GNDS and integrator input)
• Separate ferrite paths from each switch output - 4 FBs instead of FB57 and FB102 (divides impact from switching interaction/backfeed)
• Swap current steering switch, e.g. TMUX1133 and MAX4619 (might divide switch impact)
• Jitter measurement: clock, U17 D-FF, U5 switch - only externally, needs expensive equipment to resolve sub ps jitter (anyone?)

[Kleinstein]

The extra noise at 5 Hz is odd. I don't remember seeing this. It would need the integration time to be off and quite some extra delay for the rundown to get that from 50/100 Hz mains hum. The initial filter capacitors at the supply are still relatively small, but could be enough depending on the transformer voltage.

I don't remember getting significantly higher noise when measuring the internal 7 V reference. A little higher noise is expected, as the ADC uses a filtered reference (some 3 Hz LP filter), while the path to the input is less filtered. For a test one could reduce C13 (e.g. 1 µF or even 100 nF) - however this should come with slightly higher noise when measuring an external reference.  I do get higher noise when measuring an external 7 V reference. This is simply the low frequency reference noise. Here C13 would help a little.

Reducing the resistors at the integrator input comes with extra INL (U² term) from the nonlinear switch resistance. So this would only work well with lower resistance switches like the max4619. Already with 50 K and the LV4053 the turn over error is detectable (some 3 ppm) but in a range that can be corrected numerically (or avoided by a front end that uses both signs).

A point that is still a bit on the edge is the common mode voltage / supply for U12 . The OPA145 wants 3.5 V headroom from the possitive supply and with the 5.6 V zener for D9 one may get close to that limit. One might consider going a bit higher in voltage or increase R49 a bit.

A point to test could be changing the precision OP-amp (U11) at the integrator from an OPA145 to OPA140/OPA141 or OPA1641. These are faster and a little lower noise and have lower open loop Z_out. The current R10/R11 ratio is already more for the faster OP-amps.

A point that could have an effect on jitter would be a resistor in the link from clock to the µC clock input. This is to reduce effects from the µC back to the clock.

[MiDi]

A point that could have an effect on jitter would be a resistor in the link from clock to the µC clock input. This is to reduce effects from the µC back to the clock.

The first run with a 22Ω series resistor between the clock and the µC clock input gave inconclusive results.
Some measurements showed increased noise, while others remained at roughly the same level.
A second run is needed to get a clearer picture.

Meanwhile my digital assistant performed a detailed analysis and came up with a simplified best-fit noise model.
It provides some interesting insights into the individual noise sources and their contributions to the overall noise.
With the current modifications, which increased the integrator current by a factor of 3.5 (roughly halving the noise contributions from the input and reference paths), the model suggests that the dominant remaining noise sources are associated with the switching circuitry and its surrounding components, the integrator op-amp U11 OPA145 follows.
The NSD axis uses PSD-like scaling but is labelled in √PSD = NSD units, making the individual contributions to the total noise easier to visualize.

1st figure: Best-fit model compared with the measurements (only the baseline and latest measurements are shown for clarity)
2nd figure: Breakdown into the main model components: white, switching, op-amp/resistor, short-interval excess and LM399 reference noise
3rd figure: Comparison of the "white" noise contributions across operating modes and PLC settings. The U5 switch channels and integrator output driver U2 exhibit modulation-frequency-dependent noise
4th figure: Detailed breakdown of switching-related, alongside white, other contributions and total noise. All switching-related noise components depend on the modulation frequency. The short-interval excess is mainly attributed to integrator settling and increases as the fixed intervals become shorter

One limitation of the model is that it cannot reliably distinguish between U5 residual/charge-injection effects and clock/distribution jitter.
Both can explain essentially the same observed noise behavior, making them difficult to separate based on the measurements alone.

So that's the next challenge: figuring out which one actually dominates.
The obvious approach would be to try a clock with significantly lower jitter and/or a summing-node switch with substantially lower residual/charge injection.
Should be easy enough, right?